Circuit delays in integrated circuits often have to be reduced to obtain faster response times. A typical digital integrated circuit consists of multiple stages of combinational logic blocks that lie between latches that are clocked by system clock signals. For such a circuit, delay reduction must ensure that valid signals are produced at each output latch of a combinational block, before any transition in the signal clocking the latch. In other words, the worst-case input-output delay of each combinational stage must be restricted to be below a certain specification.
Weitere Kapitel dieses Buchs durch Wischen aufrufen
- Transistor Sizing Algorithms: Existing Approaches
Sachin S. Sapatnekar
- Springer US
- Chapter 3
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