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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 1/2020

07.02.2020

Trojan Detection Test for Clockless Circuits

verfasst von: Ricardo Aquino Guazzelli, Matheus Garay Trindade, Leonel Acunha Guimarães, Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos

Erschienen in: Journal of Electronic Testing | Ausgabe 1/2020

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Abstract

Clockless integrated circuits, as any type of integrated system, might today carry hardware Trojan (HT) circuits maliciously implanted in the designs during outsourced phases of fabrication. This paper proposes a testing technique dedicated to detect HTs in clockless circuits fabricated in CMOS technologies. The proposed technique applies a well-known machine learning approach – One-Class Support Vector Machine (OC-SVM) – for dealing with the particular current signature features of clockless circuits. Through simulation experiments we show the natural ability of clockless circuits in providing individual current signatures for identifying the presence of HTs. Moreover, the results demonstrate that our testing technique requires no extra circuitry or power ports to detect HTs of a few dozens of transistors in designs under Trojan test with more than 13 thousand transistors.
Vorheriger Artikel Reliability Model and Sensitivity Analysis for General Electronic Systems with Failure Types based on Non-identical Correlated Components
Nächster Artikel On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

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Metadaten
Titel
Trojan Detection Test for Clockless Circuits
verfasst von
Ricardo Aquino Guazzelli
Matheus Garay Trindade
Leonel Acunha Guimarães
Thiago Ferreira de Paiva Leite
Laurent Fesquet
Rodrigo Possamai Bastos
Publikationsdatum
07.02.2020
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 1/2020
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-020-05857-6

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