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Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, Microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.



From Thick Wafers to Ultra-Thin Silicon Chips


Chapter 1. Why Are Silicon Wafers as Thick as They Are?

Silicon wafers have been the building blocks of the electronic industry for more than 40 years. Wafer size increased from 2 in. in diameter in 1970 the wafer size increased to 300 mm in 2000, enhancing the productivity of the chip manufacturing significantly. With growing diameters, wafer thickness of wafers increased steadily, reaching 775 μm for 300-mm diameter wafers. The primary reason for this increase was the need to ensure safe wafer manufacturing without breakage and to provide sufficient mechanical and thermal stability of the wafers in IC fabrication during processing steps of lithography and heat treatments. Beyond this, silicon wafers also must meet certain defect kinetic properties in device processing, which depend on the wafer thickness as well and are crucial for device yield and economic feasibility.

Peter Stallhofer

Chapter 2. Thin Chips on the ITRS Roadmap

The International Technology Roadmap for Semiconductors (ITRS) projects decreasing chip thickness in support of three-dimensional integrated circuit (3D IC) solutions. The 3D IC technology potential is not yet fully leveraged due to insufficient scaling of the through-silicon via (TSV) pitch. Since technological limits restrict the TSV ratio at about 10:1, minimum chip thickness enables us to take full advantage of the 3D IC concept in support of continued miniaturisation (More Moore). Moreover, the excellent mechanical properties of silicon qualify ultra-thin chips for applications of silicon technology for added functionality (More than Moore).

Joachim N. Burghartz

Thin Chip Fabrication Technologies


Chapter 3. Thin Wafer Manufacturing and Handling Using Low Cost Carriers

This chapter focuses on thin wafer fabrication and processing that uses low cost sub carriers. It describes the state of the art and the technical boundaries of the application of foils for wafer support and protection. First, the thinning technology and the applied materials are described in terms of process capability and maturity. Methods of thin wafer characterization are presented. Subsequently, the impact of front end design on ultra-thin wafer manufacturing is highlighted. Finally, processes after wafer thinning that enable the “perfect” die are described.

Florian Schmitt, Michael Zernack

Chapter 4. Ultra-thin Wafer Fabrication Through Dicing-by-Thinning

The technological concept ‘dicing-by-thinning’ (DbyT) offers a new technique for die separation for ultra-thin wafers. Conventional sawing is replaced by preparation of frontside trenches and subsequent backside thinning. It will be shown that introducing plasma etched trenches allows for both preparation of ultra-thin dies of high fracture strength and for a significant increase in number of chips per wafer. It is concluded that dicing-by-thinning offers a new strategy for cost effective manufacture of very small and ultra-thin radio frequency identification (RFID) devices. Finally, a short outlook on the development of self-assembly processes for ultra-thin microelectronic components will be given.

Christof Landesberger, Sabine Scherbaum, Karlheinz Bock

Chapter 5. Thin Wafer Handling and Processing without Carrier Substrates

SiP (system in package), IC cards and RFID (radio frequency identification) tags are more commonly used in digital and mobile devices, such as cell phones, and along with such recent trends, 30–50 μm thick product die are actually used. The thinning of silicon wafers to enhance performance is also in strong demand in power devices used for power conversion, such as IGBTs (insulated gate bipolar transistors) used in solar power generation and hybrid vehicles, which are attracting attention for energy conservation and global environmental protection. This chapter introduces the process technology of making wafers thinner, which also considers wafer handling and use in the subsequent steps, in anticipation of even further thinning of wafers.

Yoshikazu Kobayashi, Martin Plankensteiner, Midoriko Honda

Chapter 6. Epitaxial Growth and Selective Etching Techniques

In this chapter a wafer-level thinning technique is presented, where, similar to what is discussed in Chapter 8, epitaxial growth of silicon (Si) determines the final chip thickness. A combination of backside grinding and selective wet chemical etching is used for thinning down the initial substrate. Since wafer bonding and grinding were thoroughly addressed in Chapters 4 and 5, this subsection deals only with the other key processing steps, namely the wet chemical etching of Si and the epitaxial growth of highly boron-doped Si required to trigger the etch selectivity. Finally, process parameters and significant results based on this technique are summarised.

Evangelos A. Angelopoulos, Alexander Kaiser

Chapter 7. Silicon-on-Insulator (SOI) Wafer-Based Thin-Chip Fabrication

Silicon-on-insulator (SOI) is a wafer substrate technology with potential to fabricate ultra-thin silicon layers and thus ultra-thin chips. The high cost of SOI wafers and technical difficulties to derive ultra-thin chips from SOI substrates so far have hindered the industrial exploitation of SOI technology for thin chip manufacturing. This chapter provides an overview of the present and past SOI technologies, a discussion about the technical difficulties in thin-chip fabrication based on SOI, and a former industrial approach as a related example.

Joachim N. Burghartz

Chapter 8. Fabrication of Ultra-thin Chips Using Silicon Wafers with Buried Cavities

In this chapter the recently introduced Chipfilm™ technology is presented. In contrast to subtractive wafer thinning techniques this technology is inherently additive, allowing for excellent control of extremely small chip thickness through epitaxial growth and for reuse of the wafer substrate. The thickness of the chips is essentially identical to the thickness of the epitaxy layer. Therefore, process cost decreases withsmaller chip thickness, while the opposite trend applies to the conventional thinning concepts. The technology consists of a pre-process module Chipfilm™, in which wafer substrates with buried cavities in the chip areas are prepared, and a minimum complexity post-process module Pick, Crack&Place™ for singulation and assembly of the ultra-thin chips. The feasibility of Chipfilm™ technology is demonstrated for 20-μm thin chips mounted and interconnected on foil and exposed to tensile stress through bending to radii down to 20 mm. The device parameters and parameter statistical variations are well comparable to those achieved on bulk wafers for the given 0.8-μm CMOS technology.

Martin Zimmermann, Joachim N. Burghartz, Wolfgang Appel, Christine Harendt

Add-on Processing


Chapter 9. Through-Silicon Vias Using Bosch DRIE Process Technology

Silicon deep reactive ion etching (DRIE) is having a great effect on micro-electro-mechanical systems technology (MEMS) and quite recently also on memory devices and through-silicon via (TSV) etch applications. Nowadays, it is an established fabrication process within the MEMS field. The basic technology was originally developed at Bosch in the early 1990s. At that time, classical wet etching in KOH was the state-of-the-art technology, with design options like the silicon vias and also many others remaining unthinkable. With the Bosch DRIE process it became possible to overcome the design restrictions and compatibility problems related to the old silicon wet etching technology. The etching performance of the Bosch process is not reached by any wet etchant or other microstructuring technology. Today, after more than a decade of Bosch process plasma etching technology shaping the MEMS field, it is emerging also as a new enabler in other areas, e.g., for extremely precise high aspect ratio TSVs for stacking memory chips and other purposes. The Bosch process has evolved throughout the years thanks to continuing progress in process and hardware development. Today a broad supplier base is supporting DRIE customer needs in many application areas, with the industry’s high-density plasma equipment and process know-how all over the world.

Franz Laermer, Andrea Urban

Chapter 10. Through-Silicon via Technology for 3D IC

Three-dimensional (3D) integration complements semiconductor scaling in enabling higher integration density as well as heterogeneous technology integration. Through 3D chip stacking it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realised using advanced CMOS technology nodes but may also exploit a wide variety of device technologies to optimise system performance. A key technology is the possibility for establishing electrical connections through the bulk of the silicon substrates on which semiconductor devices are realised. These connections are generally referred to as through-silicon-vias, or TSVs. A wide variety of technologies has been and continue be being proposed to realise such TSV connections. In this chapter, a classification of 3D technologies is proposed based on the system-level interconnect hierarchy. Different technology options for realising TSV structures are put forth and the main technological challenges discussed.

Eric Beyne

Chapter 11. 3D-IC Technology Using Ultra-Thin Chips

Various generic methods for the three-dimensional (3D) integration of integrated circuits (ICs) are discussed. All these methods rely on ultra-thin chips. Wafer-to-wafer bonding, chip-to-wafer bonding, multichip-to-wafer bonding and reconfigured wafer-to-wafer bonding are described and compared. Several test chips fabricated by that use some of those concepts are briefly mentioned. Finally, specific concerns related to 3D-IC integration that use ultra-thin chips are indicated.

Mitsumasa Koyanagi

Chapter 12. Substrate Handling Techniques for Thin Wafer Processing

This chapter describes the necessity that carrier techniques be developed for thin wafer handling and processing. After an explanation on the main requirements for handle substrate techniques, we give an overview on the following temporary bonding techniques and mechanisms: thermoplastic adhesives, release layers, soluble glues, reversible tapes, mechanical debonding and electrostatic bonding. Finally, we conclude that the development of appropriate carrier techniques for ultra-thin wafers represents a key element of future thin wafer technology.

Christof Landesberger, Sabine Scherbaum, Karlheinz Bock

Assembly and Embedding of Ultra-Thin Chips


Chapter 13. System-in-Foil Technology

Systems-in-foil are an emerging new class of flexible electronic products in which complete systems are integrated in thin polymeric foils. First, a brief overview of the basic material choices and fabrication concepts will be given. Then, more detailed attention will be paid to the approaches of heterogeneous integration of thin chips. The different integration process flows and challenges and application fields will be described for three distinct areas: (1) ultra-thin chip packages with high density interconnects; (2) embedded circuitries for low cost flip-chip attachment to flexible substrates; and (3) embedded optical chips. It is important also to balance secondary material properties like thermal expansion, elastic moduli and adhesion strengths of different materials used to facilitate reliable operation of systems-in-foil under mechanical bending and at varied temperatures.

Andreas Dietzel, Jeroen van den Brand, Jan Vanfleteren, Wim Christiaens, Erwin Bosman, Johan De Baets

Chapter 14. Chip Embedding in Laminates

This chapter provides an overview of the technology of embedding chips into laminates. The motivation, an overview of technological approaches and the challenges will be outlined. One of the technologies will be described in more detail through a case of an application. Finally a technological outlook is given in consideration of the innovations the embedded technology could make possible.

Andreas Kugler, Metin Koyuncu, André Zimmermann, Jan Kostelnik

Chapter 15. Handling of Thin Dies with Emphasis on Chip-to-Wafer Bonding

Thin dies with all their advantages bear various new challenges for die handling during die attach or flip-chip processes. The changed properties, like increased brittleness as well as higher flexibility of the dies, have to be addressed accordingly with new concepts for effective detachment from the wafer tape, low stress handling during transfer and adhesion processes that need to be chosen more carefully for each application. In this chapter various ejection principles and handling tool examples are described together with a few product applications that have gained in importance for mass production because of the development towards ultra-thin dies. Three-dimensional integration using through silicon vias and dies embedded in polymer are two examples of applications that became possible only by the introduction of thin dies.

Fabian Schnegg, Hannes Kostner, Gernot Bock, Stefan Engensteiner

Chapter 16. Micro Bump Assembly

One of the key technologies for enabling 3D integration of semiconductor devices is the micro bump based interconnect joining that allows silicon dies with through-silicon vias (TSVs) to be stacked on each other. In order to achieve a high level of integration, the pitch and dimensions of these micro bumps also need to be reduced. Significant assembly challenges need to be overcome in order to accomplish successful yielding micro bump assemblies. In this chapter, the assembly aspects of micro bump fabrication, joining and underfill integration are discussed. The metallurgical fundamentals of micro bump formation are discussed in order to give insight into the choice of interconnect bonding method, the under bump metallisation and the micro bump as such and the impact of these on the stacking approach. Finally, various stacking schemes for 3D integration are considered and their relative advantages and drawbacks are discussed.

Paresh Limaye, Wenqi Zhang

Characterization and Modelling


Chapter 17. Mechanical Characterisation and Modelling of Thin Chips

In order to ensure reliable products, electronic, as well as mechanical, properties of thin chips must also be characterised. In particular, the strength of silicon devices is an important key for improvement of the yield and avoidance of the fracture of silicon chips and devices in manufacturing and application, respectively. This chapter discusses strength parameter in detail and how strength of thin silicon chips can be analysed. Besides theoretical relations, examples of strength behaviour of thin silicon chips are presented regarding different manufacturing steps.

Stephan Schoenfelder, Joerg Bagdahn, Mattias Petzold

Chapter 18. Structure Impaired Mechanical Stability of Ultra-thin Chips

Flexibility of ultra-thin chips is an important condition for applications in flexible electronics. Especially, mechanical reliability of ultra-thin chips is a key factor generally determining the final performance and reliability of a flexible electronics product. Structures and designs implemented on the chips are the elements that weaken the mechanical stability of the final product. In this chapter the excellent mechanical strength of 20-μm thin silicon chips produced by the Chipfilm


technology is discussed. The influences of different parameters, such as the number of anchors per chip edge, the backside porous silicon and the topography formed by CMOS integration, on their mechanical reliability are investigated by means of uniaxial bending tests. The experimental results are statistically evaluated by the Weibull theory, in which the resulting failure stress data are used to obtain the fracture strength and estimate failure origins of the tested ultra-thin chips.

Tu Hoang, Stefan Endler, Christine Harendt

Chapter 19. Piezoresistive Effect in MOSFETS

Mechanical deformation changes the silicon material’s electrical resistivity (Smith, Phys Rev 94(1):42–49, 1954). This is an important property of the material. The effect known as ‘piezoresistive’ has found many applications over time. In micro-electro-mechanical systems (MEMS), for example, it has enabled the integration of pressure sensors with complementary metal-oxide semiconductor (CMOS) circuits that translate the stress into voltage signals. The piezoresistive effect has been also observed and studied in the metal-oxide-silicon field effect transistor (MOSFET), the principal component of a CMOS integrated circuit (IC). In transistors the strain affects the mobility of the carriers and as a result the drain current and the speed of the transistor. Although scaling tends to achieve its limitations, the need to further increase the MOSFET performance by having more power and speed remains. Based on mobility enhancement due to the stress/strain applied to the MOSFET channel, the ‘strained Si’ technique has been chosen as a new degree of freedom to further improve MOSFET performance and to defeat scaling limitations. In this chapter we discuss aspects related to the piezoresistive effect in bulk Si and its modifications in MOSFET Si inversion layer. We analyse the strain effects on Si electronic band structure and its transport properties. Piezoresistive coefficient values from literature for bulk Si and MOSFETs under uniaxial strain are presented and compared.

Nicoleta Wacker, Harald Richter

Chapter 20. Electrical Device Characterisation on Ultra-thin Chips

For ultra-thin chips (<20 μm) intended for use in flexible systems, external mechanical stress is inevitably relevant. Because mechanical stress can directly affect the electrical behaviour of semiconductor materials, it is vital to examine the effect of bending on different electrical devices and circuits to anticipate their behavior in flexible systems. Moreover, this effect can be well-used for sensor applications. Such applications also demand in-depth investigation of the mechanical deformation effect on different devices and circuits fabricated on ultra-thin chips. In this chapter various usable chip bending and electrical measurement techniques for devices are discussed. We also elaborate on limitations and error factors associated with applied characterisation methods, along with possible solutions apprehended from our experiences with ultra thin chip characterisations at Institut für Mikroelektronik Stuttgart (IMS Chips).

Mahadi-Ul Hassan, Horst Rempp, Harald Richter, Nicoleta Wacker

Chapter 21. MOS Compact Modelling for Flexible Electronics

Circuit design in flexible electronics should account for shifts in metal-oxide semiconductor (MOS) characteristics with the mechanical strain induced by substrate bending. Apart from the standard process and layout strain sources, externally applied strain in flexible electronics varies with bending direction and radius. The physical compact models for the strain effects on semiconductor band structure and carrier mobility due to substrate bending are derived in this chapter from basic deformation potential theory. It is demonstrated how existing MOS compact models could be extended for bending-induced strain effect by modification of the set of material model parameters controlling the semiconductor band structure and carrier mobility.

Slobodan Mijalković

Chapter 22. Piezojunction Effect: Stress Influence on Bipolar Transistors

The saturation current of a bipolar transistor changes considerably under the influence of mechanical stress. This change is called the

piezojunction effect

. It is unwanted in precision circuits such as bandgap references, which usually become stressed during fabrication, packaging or use. However, it can be used to good advantage in mechanical sensors. The effect is strongly anisotropic, depends on the transistor type (




) and is in many aspects similar to the piezoresistive effect for resistors. The piezojunction effect can be modelled similarly by a MacLaurin series expansion. For stresses below 200 MPa, an expansion up to the second order is appropriate. For lower stresses a first-order description can be used. This description can be displayed in polar plots that may be used to find optimum values. The coefficients of the expansion are determined by the piezojunction coefficients, which are material parameters. The piezojunction coefficients depends on stress-induced changes in both the mobility and the intrinsic carrier concentration. They can be determined from measurements but also from calculations using band deformation theory.

J. Fredrik Creemer, Patrick J. French

Chapter 23. Thermal Effects in Thin Silicon Dies: Simulation and Modelling

Detailed three-dimensional (3D) numerical thermal simulations are employed to clarify the influence of the key technological parameters and material properties on the thermal behaviour of ultra-thin chip stacking modules, wherein the heat removal from the thinned active dies is considerably hampered by benzocyclobutene layers. In particular, the impact of heat source area and thickness of silicon dies and benzocyclobutene layers is investigated in structures with one, two, and three thin silicon dies. The adoption of compact thermal models is then suggested as a solution to reduce the computational resources required to numerically analyse stacked-die modules.

Niccolò Rinaldi, Salvatore Russo, Vincenzo d’Alessandro

Chapter 24. Optical Characterisation of Thin Silicon

This chapter presents the optical characteristics of thin silicon. It starts with the absorption of irradiation, discusses the efficiency potential for thin solar cells and introduces the quantum efficiency. The chapter further discusses the advantages of vertical versus lateral arrangement of the pn-junction and introduces laser processing of silicon, which allows, e.g. for low temperature contactless emitter formation.

Michael Reuter, Sebastian J. Eisele



Chapter 25. Thin Chips for Power Applications

Thin chips for power applications are the key enabler for energy efficiency. This chapter will view low voltage metal oxide semiconductor field effect transistors (MOSFETs), IGBTs (insulated gate bipolar transistors) and FWDs (free wheeling diodes). For these the trend to ultra-thin power transistor chips (20 μm thickness) and the resulting electrical and thermal benefits by chip thickness reduction is described. Further the influence of thin chips on product definition and application especially for automotive smart power devices is pointed out. Thin chips technology for power applications allow an increase in efficiency and new packaging processes of semiconductor devices. The application benefits include reduced area requirements for the same performance and new packaging processes.

Kurt Aigner, Oliver Häberlen, Herbert Hopfgartner, Thomas Laska

Chapter 26. Thinned Backside-Illuminated (BSI) Imagers

Backside-illuminated (BSI) imagers are becoming popular due to their enhanced light sensitivity. During their fabrication advanced Si wafer thinning is used in combination with backside surface passivation techniques. In this section both technology for thin (hybrid) backside-illuminated imagers as well as the trade-offs they present between quantum efficiency and crosstalk are discussed and illustrated, with the use of imec imager results.

Koen De Munck, Kyriaki Minoglou, Piet De Moor

Chapter 27. Thin Solar Cells

This chapter outlines the advantages of thin crystalline silicon solar cells, gives an overview on the current status in research and development on solar cells with thicknesses below 50 μm and describes the current developments. The material utilisation of different wafer fabrication methods is discussed, and an overview on applications for thin and hence flexible solar cells is given.

Michael Reuter

Chapter 28. Bendable Electronics for Retinal Implants

This chapter focuses on sub-retinal chip implants, a direct replacement technique of malfunctioning photoreceptors in the retina of the human eye. The physical space available requires the application of a thin chip with thickness of 30–50 μm. These chips are unpackaged and thus need to be passivated to warrant long-term stability and reliability. Both passive and active chip design concepts are discussed.

Heinz-Gerd Graf

Chapter 29. Thin Chip Flow Sensors for Nonplanar Assembly

A thermoelectric mass flow rate sensor on a 10-μm thick polyimide foil for nonplanar assembly has been developed. For principal operation of thin film sensors a few hundred micrometres thick substrate (usually a 525-μm or 380-μm thick silicon wafer) is not necessary and might be detrimental for system integration, e.g., it could cause turbulences due to step in flow channel. A fabrication has been developed by removing the functional layers from the silicon substrate and transferring them onto a 10-μm thick polyimide foil. The sensor foil has been integrated on different materials by means of flip chip mounting and tested on its electrical and mechanical characteristics with air as flowing medium. Here, it was shown that thermoelectric flow sensors on polymer foils have comparable characteristics to flow sensors on silicon substrates. The outcome of this development is a highly integrated flow sensor on a polymer foil, which can be placed on planar, nonplanar as well as flexible surfaces and still has a comparable performance to thermoelectric flow sensors on silicon substrate.

Hannes Sturm, Walter Lang

Chapter 30. RFID Transponders

Today, radiofrequency identification (RFID) is omnipresent and used in a vast amount of applications, ranging from pet registration to manufacturing logistics. As each application has its own requirements, a lot of different RFID systems have been developed in the past. The only similarity in these systems is that they consist of two basic elements, which are an interrogator and a so-called ‘transponder’. This chapter will first provide a brief overview of RFIDs and shows typical applications and their special requirements. Finally, the chapter focuses on existing ultra-thin RFID transponders and new developments that will yield small, thin RFID transponders.

Cor Scherjon

Chapter 31. Thin Chips for Document Security

This article underscores the importance of thin silicon for the development of new RFID security products. Quality requirements are presented that show how the utilisation of thin silicon enables new business opportunities. A presentation of some typical RFID applications, based on thin silicon, gives an impression of thin silicon integration into RFID security products.

Thomas Suwald

Chapter 32. Flexible Display Driver Chips

Rapid advancements in the field of flexible display have lifted expectations of the availability of full-flexible display products in near future. A full-flexible, paperlike display requires ultra-thin driver chips embedded in the same flexible substrate. This reduces external connections and cost of product, and it increases system reliability. Organic materials, hydrogenated amorphous silicon (a-Si:H), polysilicon and single-crystal silicon are potential candidates for ultra-thin chips, each with its pros and cons. High mobility transistors are indispensible for video streamings. Threshold instability and self-heating issues demand proper addressing. Different placement schemes of driver chips around TFT matrix and various driving waveforms can be employed to drive heavy loads, especially in case of large-size displays. Technical obstacles must be eliminated in order to realise mass productions of full-flexible display systems.

Ali Asif, Harald Richter

Chapter 33. Microwave Passive Components in Thin Film Technology

This chapter is dedicated to a theoretical investigation of the electrical behaviour of inductors and transmission lines integrated on thin silicon wafers. Using electromagnetic simulations, it is shown that thinning a standard silicon substrate to ˜20–70 μm yields a ˜20–30% increase in the maximum quality factor and resonance frequency of typical integrated spiral inductors. This improvement is due to a higher spreading substrate resistance between the inductor and the physical ground. However, further improvement of the quality factor requires substrates thinned to several microns in order to reduce the effect of stray electric fields induced between different points on the conductor, e.g., between adjacent windings. In the case of coplanar waveguide and microstrip transmission lines, significant improvement in device quality is only observed when silicon thickness reaches values below 10 μm. On highly conductive silicon, the behaviour of inductors and transmission lines as a function of substrate thickness becomes strongly dependent on silicon resistivity. In particular, thinning substrates with a resistivity in the 0.01–2 Ω-cm range may even have an adverse effect on device performance.

Behzad Rejaei

Chapter 34. Through-Silicon via Technology for RF and Millimetre-Wave Applications

This chapter focuses on some of the radiofrequency (RF) and millimetre-wave (MMW) applications that a through-silicon via (TSV) technology can enable. We will first discuss a grounded TSV application for a RF wireless communication power amplifier that is in mass production. A grounded TSV is essentially a metal connection that takes the active device interconnect to a package ground without needing to go through wire bond. A tungsten-filled grounded TSV delivers over 75% reduction in inductance compared to a traditional wire bond, thus enabling higher frequency applications in silicon technology. Such a grounded TSV is seamlessly integrated into a 350-nm SiGe BiCMOS. Next we show feasibility on insulated TSV that is utilised in a digital technology for high speed I/O functions, such as, in an advanced microprocessor. The insulated TSV sits in a 3D-IC carrier silicon chip that is made compatible with standard 90-nm high performance CMOS processing. The TSV arrays are designed to provide minimal resistance and inductance with excellent yield and breakdown voltage characteristics. A commercial application of this concept is for the emerging 100-Gb Ethernet that requires almost 1 Tbps data transmission between ICs. This concept of insulated via in a 3D-IC environment is then extended to a 130-nm MMW SiGe BiCMOS technology. We introduce the concept of a Wilkinson power divider that can be utilised in a 60-GHz phased array radar system.

Alvin Joseph, Cheun-Wen Huang, Anthony Stamper, Wayne Woods, Dan Vanslette, Mete Erturk, Jim Dunn, Mike McPartlin, Mark Doherty


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