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1987 | Buch

VLSI CAD Tools and Applications

herausgegeben von: Wolfgang Fichtner, Martin Morf

Verlag: Springer US

Buchreihe : The International Series in Engineering and Computer Science

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SUCHEN

Über dieses Buch

The summer school on VLSf GAD Tools and Applications was held from July 21 through August 1, 1986 at Beatenberg in the beautiful Bernese Oberland in Switzerland. The meeting was given under the auspices of IFIP WG 10. 6 VLSI, and it was sponsored by the Swiss Federal Institute of Technology Zurich, Switzerland. Eighty-one professionals were invited to participate in the summer school, including 18 lecturers. The 81 participants came from the following countries: Australia (1), Denmark (1), Federal Republic of Germany (12), France (3), Italy (4), Norway (1), South Korea (1), Sweden (5), United Kingdom (1), United States of America (13), and Switzerland (39). Our goal in the planning for the summer school was to introduce the audience into the realities of CAD tools and their applications to VLSI design. This book contains articles by all 18 invited speakers that lectured at the summer school. The reader should realize that it was not intended to publish a textbook. However, the chapters in this book are more or less self-contained treatments of the particular subjects. Chapters 1 and 2 give a broad introduction to VLSI Design. Simulation tools and their algorithmic foundations are treated in Chapters 3 to 5 and 17. Chapters 6 to 9 provide an excellent treatment of modern layout tools. The use of CAD tools and trends in the design of 32-bit microprocessors are the topics of Chapters 10 through 16. Important aspects in VLSI testing and testing strategies are given in Chapters 18 and 19.

Inhaltsverzeichnis

Frontmatter
1. VLSI Design Strategies
Abstract
The growing complexity of VLSI chips creates a need for better CAD tools and data management techniques. The rapidly changing nature of the field requires a modular toolbox approach — rather than a fixed monolithic design system — and the involvement of the designer in the toolbuilding process. A short overview over the Berkeley design environment and our recent Synthesis Project is also given.
Carlo H. Séquin
2. Introduction to VLSI Design
Abstract
In recent years, modern VLSI technology has made possible the realization of complex digital systems on a single silicon chip. The ability to compress much digital logic complexity onto a single chip has provided the means to achieve substantial cost reductions, making this technology very attractive for designers of custom systems.
Jonathan Allen
3. Simulation Tools for VLSI
Abstract
Simulation plays an important role in the design of integrated circuits. Using simulation, a designer can determine both the functionality and the performance of a design before the expensive and time-consuming step of manufacture. The ability to discover errors early in the design cycle is especially important for MOS circuits, where recent advances in manufacturing technology permit the designer to build a single circuit that is considerably larger than ever before possible. This paper reviews the simulation techniques which are commonly used for the simulation of large digital MOS circuits.
Christopher J. Terman
4. Aspects of Computational Circuit Analysis
Abstract
A hierarchical formulation of the differential-algebraic systems describing circuit behavior is presented. A number of algorithms that have proven effective are reviewed. These include multidimensional splines that preserve monotonicity, sparse direct and iterative methods for the linear equations, damped-Newton and Newton-iterative techniques for the nonlinear equations, continuation methods, and low-order time-integration formulae. Some aspects of time macromodeling are described.
W. M. Coughran Jr., Eric Grosse, Donald J. Rose
5. VLSI Circuit Analysis, Timing Verification and Optimization
Abstract
In this paper, we give an overview of the state-of-the-art in Circuit Analysis, Timing Verification, and Optimization. Emphasis is given to circuit analysis, timing verification and optimization since simulation is covered by C. Terman in this book. Also, the optimization of large circuits is receiving new attention due to the need for timing performance improvement in silicon compilation.
Albert E. Ruehli, Daniel L. Ostapko
6. CAD Tools for Mask Generation
Abstract
CAD Tools for Mask Generation is a general title that refers to Computer-Aided Design software that produces as its output mask-level descriptions of integrated circuits. The current state-of-the-art for general mask generation in a custom design environment is that of symbolic design. So this chapter is about symbolic design and how it generates a mask. Included are discussions of design capture, circuit description languages, compaction and technology encapsulation all in the context of the symbolic design environment. General overviews are not given in most cases. Instead, a feel for this technology is given through specific examples of a system most familiar to the author.
Jonathan B. Rosenberg
7. Design and Layout Generation at the Symbolic Level
Abstract
A pipeline or three tools for the construction or high-quality macro modules or library cells is described. TOPOGEN is a synthesis tool that takes a logic description at the gate level and converts it into a symbolic layout or a static CMOS circuit on a virtual (coarse) grid. EDISTIX is an interactive virtual grid editor for the creation or modification of symbolic sticks diagrams. ZORRO is a two-dimensional compactor using the concept of ‘Zone refining’ to generate the mask geometry from the symbolic layout. The generation or the final layout of a cell is a two-step process using an intermediate symbolic representation on a virtual grid. In this intermediate state, the user can interactively make changes.
Carlo H. Séquin
8. Overview of the IDA System: A Toolset for VLSI Layout Synthesis
Abstract
The Integrated Design Aides (IDA) toolset is a set of VLSI CAD software programs that have been developed to make the most effective use possible of a designer’s time. IDA incorporates a number a layout synthesis tools capable of generating both structured circuits, such as ALU’s, and random logic. The system centers around a constraint-based, symbolic language called IMAGES and a compacter methodology. This paper describes IDA, its capabilities, techniques, and status.
Dwight D. Hill, Kurt Keutzer, Wayne Wolf
9. CAD Programming in an Object Oriented Programming Environment
Abstract
ns is an integrated design system which unifies a broad spectrum of different ic design tools. ns currently contains facilities for schematic capture, electrical level simulation, switch level simulation, virtual grid symbolic layout with compaction and pitch-matching, automatic standard cell layout generation, floorplanning, and network comparison between the layout and the schematic representations of a design. Designs may be entered either through a graphical editor or via procedural generation. All facilities of the system are accessible through a single graphical editor; they are all driven from a single data base and they may be manipulated through a single procedural interface.
James Cherry
10. Trends in Commercial VLSI Microprocessor Design
Abstract
Here is how commercial VLSI microprocessors have been designed, starting with the Motorola MC68000 (1977–79). I impart the design method and say what software tools were used. Here is how the chips, methods, and tools have evolved. I project the trends. In 1977, logic design was done with pencil and paper. Design verification consisted of programs simulating small sections of a chip and of TTL breadboards. Today (1986), logic design is still done with pencil and paper, but it is entered into a computer using an ordinary text editor. Design verification programs then check this text file. In the next 5 to 10 years, logic design will still be done with pencil and paper, but it will be entered into the computer with a specialized editor. Design verification will stay the same. I don’t think the level of automation will increase significantly for commercial VLSI microprocessor design. The design tools will run faster because the computers they run on will be faster. There will he more computers. So there will be more instances of the use of design tools. But for commercial microprocessors, I don’t think logic design tools will do substantially more than they do today. The opinions expressed are solely those of the author. These opinions do not reflect positions held by the IBM Corporation.
Nick Tredennick
11. Experience with CAD Tools for a 32-Bit VLSI Microprocessor
Abstract
As the complexity of VLSI devices increases, so does the need to rely on computer aided design (CAD) methods. As VLSI designs grow they push the limits of the CAD tools, and in some cases require new approaches to design and verification. This paper reports on experiences with a particular approach taken to design a 170,000 transistor single chip CMOS microprocessor. The chip was an implementation of the Bell Labs C-Machine 1, 2 architecture, code-named CRISP (C-Machine Reduced Instruction Set Processor) during its design. The major design tools used are described along with pleasant and unpleasant surprises in their use. Problems with more traditional approaches due to the increased size of designs are discussed.
David R. Ditzel, Alan D. Berenbaum
12. Overview of a 32-Bit Microprocessor Design Project
Abstract
This paper will attempt to give an overview of a large microprocessor design project. Its purpose is not so much to describe a particular machine, but rather to describe the design process. It will present the design approaches taken and the design tools used or created during the project, and will cover topics such as the division of work, problem areas and important results. However, in order to properly set that discussion in perspective, a brief description of the microprocessor will also be given.
Pat Bosshart
13. Architecture of Modern VLSI Processors
Abstract
In recent years, the focus of VLSI architecture effort has been primarily on the tradeoffs possible in new microprocessor instruction sets. The result has been a collection of machines with new streamlined instruction sets, and new hardware subsystems tuned to maximize performance. This leaves many designers with a difficult problem: how to apply these new ideas within the constraints of an existing instruction set. Moreover, as the industry converges on faster internal architectures for microprocessors, the design problem changes to address more system-level issues, such as caching structures, I/O, memory interfaces. and peripherals. Traditionally, it has been difficult to analyze these system-level issues in detail, and as a result, many machines have been built based on intuition or incomplete data. However, the availability of existing microprocessors, and rapid advances in CAD techniques, have made possible experiments that help guide design decisions with more solid data.
Priscilla M. Lu, Don E. Blahut, Kevin S. Grant
14. A Comparison of Microprocessor Architectures in View of Code Generation by a Compiler
Abstract
A high-level programming language mirrors an abstract computing engine, implemented by a combination of a concrete computer and a compiler. The pair should therefore be carefully tuned for optimal effectiveness. Otherwise, compromises between more complex compiling algorithms and less efficient compiled code are inevitable. We investigate three processor architectures and analyze their effectiveness for use with a high-level language. The conclusion: neither particularly sophisticated nor drastically “reduced” architectures are recommended. Instead, the proven and pivotal mathematical concepts of regularity and completeness hold the key to performance and reliability.
N. Wirth
15. Fault Tolerant VLSI Multicomputers
Abstract
An approach is presented to increasing the reliability of future high-end systems beyond what is possible with technological solutions alone. The system consists of computation nodes and communication nodes, interconnected by high-speed dedicated links. These components are relied upon to detect errors while system level protocols are used for error recovery and reconfiguration. The use of duplication and matching for implementing the self-checking nodes allows us to restrict a detailed analysis of the impact of all possible faults to the comparator, a circuit that can be implemented in a relatively straight-forward way in NMOS or CMOS technology.
Carlo H. Séquin, Yuval Tamir
16. The VLSI Design Automation Assistant: An IBM System/370 Design
Abstract
The Design Automation Assistant, DAA, is a knowledge-based expert-system that generates a technology-independent list of operators, registers, data paths and control signals from an algorithmic description of a VLSI system. This chapter shows the generality of design knowledge in the DAA by comparing and contrasting an IBM System/370 designed by an expert human designer, Claud Davis, against the design produced by the DAA. For each difference, possible changes in the CMU/DA system and the DAA are discussed. Davis himself felt the design produced by the DAA exhibited the quality he would expect from one of his better designers.
T. J. Kowalski
17. Higher Level Simulation and CHDLs
(Computer Hardware Description Languages)
Abstract
This paper gives an introduction to Computer Hardware Description Languages (CHDLs) and their application in early phases of the VLSI design process. It first gives a survey on objectives of its use in simulation. Then it briefly introduces a subset of a modern register transfer language (RT language). Finally it gives a survey on various CHDL-based CAD tools and its linkage to physical design, as well as its integration into CAD environments.
Reiner W. Hartenstein, Udo Welters
18. New Trends in VLSI Testing
Abstract
Test data generation for complex integrated circuits or today printed circuits requires an hierarchical approach including the possibility of using diversified types of descriptions (behavioral, functional, structural) as well as diversified test generation methods for elementary blocks.
G. Saucier, C. Bellon, M. Crastes De Paulet
19. VLSI Testing: DFT Strategies and CAD Tools
Abstract
The increasing complexity of the design primitives used and the higher degree of integration now possible are two factors that impede testability. This is due to the higher number of gates which is not matched by an adequate increase in pin count. Using CAD tools, the cost of designing such “more complicated chips” can of course be kept within reasonable limits, but the cost of test preparation will explode due to the level of complexity. Another fact is that semicustom design is on the increase. Bearing in mind that the intention underlying semicustom design is to achieve low-volume production of a great variety of circuits in a very short turn-around time, it is obvious that the factors of high cost and long test preparation time are becoming more critical, as compared with universal chips produced in large quantities. Thus it is essential to automate test preparation by using adequate CAD tools, such as automatic test pattern generation (ATPG). The basis for the effectiveness of these tools is a strict design for testability (DFT), even if the chip area becomes somewhat larger.
M. Gerner, M. Johansson
Metadaten
Titel
VLSI CAD Tools and Applications
herausgegeben von
Wolfgang Fichtner
Martin Morf
Copyright-Jahr
1987
Verlag
Springer US
Electronic ISBN
978-1-4613-1985-6
Print ISBN
978-1-4612-9186-2
DOI
https://doi.org/10.1007/978-1-4613-1985-6