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Über dieses Buch

One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design". As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Yield Estimation and Prediction

Abstract
Due to inherent fluctuations in any integrated circuit manufacturing process, the yield (which is nominally viewed as the ratio of the number of chips that perform correctly, i.e., meet all performance specifications, to the number of chips manufactured) is always less than 100%. As the complexity of VLSI chips increases, and the dimensions of VLSI devices decrease, the sensitivity of performance to process fluctuations increases, thus further reducing the manufacturing yield. Since profitability of a manufacturing process is directly related to yield, the search for computer-aided methods for maximizing yield through improved design methods and control of the manufacturing process has intensified dramatically.
Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

Chapter 2. Parametric Yield Maximization

Abstract
As indicated in the previous chapter, parametric yield is a function of the nominal values of the process controls and or the layout. Thus we can consider choosing a nominal design point that maximizes the number of circuits which meet a given performance specification. This approach to yield maximization is called design centering. Prior to 1977, Monte Carlo methods [48], [28], albeit crude and expensive, had been the technique primarily used for design centering. Bandler et al.. [6] then proposed a design centering procedure that was directly related to classical nonlinear programming methods [33]. This approach was based upon selecting for each individual problem, a scalar objective functional which when minimized, inscribed a hypercube in the “feasible region” R of the n-dimensional parameter space.2 However, the nonlinear programming approach does not attempt to approximate the boundary of the feasible region, but only determines points on this boundary. As will be seen below, an explicit approximation of the boundary of the feasible region is useful for solving a variety of other statistical design problems [89, 121, 16] as well as allowing one to obtain a Monte Carlo estimate of the yield at a reduced computational cost.
Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

Chapter 3. Statistical Process Simulation

Abstract
In the last chapter we indicated that yield maximization methods, which take into account inherent fluctuations in the IC manufacturing process, must be supported by statistical process and device simulation. It will also be demonstrated in the following chapters of this book that such simulation is a necessary ingredient not only for circuit design but also for process and device development, as well as IC process diagnosis and control. This chapter describes the statistical process and device simulator FABRICS , which can mimic the stochastic nature of the manufacturing process. This simulator is based on concepts first proposed in [59], and then in [61, 65] and [83]. FABRICS consists of two major parts: a process simulator and a device simulator. The models implemented in FABRICS allow for the statistical simulation of typical semiconductor devices manufactured by a variety of fabrication processes.
Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

Chapter 4. Statistical Analysis

Abstract
This chapter describes several examples of the statistical analysis of IC performance. The first section is devoted to the description of the new approach to statistical timing analysis which offers a very significant improvement in the speed of evaluating the timing behavior of digital MOS IC’s. This approach is especially well suited for the statistical design purposes such as design centering or worst-case design. The latter is the subject of the next section in which the worst-case analysis is formalized. A software system, WORCAN, is also described in this section together with some computational examples. Finally, the last section describes an approach to statistical optimization of the functional blocks of IC’s. The optimization is carried out in terms of both layout and process control parameters. FABRICS is used in all the examples in this chapter to generate the data for statistical analysis.
Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

Chapter 5. Functional Yield

Abstract
In Chapter 1 we observed that functional yield losses, i.e., yield losses that are found during functional testing, are primarily due to local process disturbances (also called spot defects , point defects or random defects ). Models that relate functional yield losses to a statistical characterization of spot defects have been studied since the early 1960’s. Such models were developed to predict manufacturing yield by using defect densities extracted from an existing product. These models proved successful [111] for memory designs where defect densities extracted from one memory design could be used to predict yield of another memory design. The accuracy of predicting yield for this case was satisfactory because the topologies of the two memories were usually similar.
Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

Chapter 6. Computer-Aided Manufacturing

Abstract
In this chapter we present a methodology for statistical process control of VLSI fabrication processes. We formally introduce a general framework for a Computer Aided Manufacturing system that can be used to monitor, diagnose and control IC manufacturing. We formulate the task of process control as one of profit maximization and develop the associated objective function and the constraints for a number of manufacturing scenarios.
Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas

Backmatter

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