VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications

This research article presents an implementation of high-performance Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) core for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM)-based applications. The radix-2 butterflies are implemented using arithmetic optimization technique which reduces the number of complex multipliers involved. High-performance approximate multipliers with negligible error rate are used to eliminate the power-consuming complex multipliers in the radix-2 butterflies. The FFT/IFFT prototype using the proposed high-performance butterflies are implemented using Altera Quartus EP2C35F672C6 Field Programmable Gate Array (FPGA) which yields 40% of improved logic utilization, 33% of improved timing parameters, and 14% of improved throughput rate. The proposed optimized radix-2-based FFT/IFFT core was also implemented in 45-nm CMOS technology library, using Cadence tools, which occupies an area of 143.135 mm² and consumes a power of 9.10 mW with a maximum throughput of 48.44 Gbps. Similarly, the high-performance approximate complex multiplier-based optimized FFT/IFFT core occupies an area of 64.811 mm² and consumes a power of 6.18 mW with a maximum throughput of 76.44 Gbps.