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Erschienen in:
Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation Kapitel lesen Erstes Kapitel lesen

2017 | OriginalPaper | Buchkapitel

2. VLSI Test and Hardware Security Background for Hardware Obfuscation

verfasst von : Fareena Saqib, Jim Plusquellic

Erschienen in: Hardware Protection through Obfuscation

Verlag: Springer International Publishing

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Abstract

This chapter discusses the fundamental concepts of design and testing and their role in hardware obfuscation. It outlines the traditional design flow of integrated circuits and assesses the vulnerabilities associated with the verification techniques and testing structures that can expose the design details and help reverse-engineer the functionality. A survey of security enhancement schemes has been presented. Furthermore, different classifications of hardware obfuscation have been discussed that cover the associated vulnerabilities of key management in nonvolatile memories (NVMs). The review of nonvolatile memories, emerging technologies and hardware-based cryptographic primitives, physical unclonable functions (PUFs) and true random number generators (TRNGs) and their use in hardware obfuscation techniques has been deliberated.

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Vorheriges Kapitel Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation
Nächstes Kapitel Logic Encryption
Literatur
1.
Zhuang X, Hsien-Hsin TZ, Lee S, Pande S (2004) Hardware assisted control flow obfuscation for embedded processors. In: Proceedings of international conferences on compilers, architecture, and synthesis for embedded system, pp 292–302
2.
Rajendran J, Sinanoglu O, Karri R (2013) Is split manufacturing secure? In: Proceedings of the IEEE design, automation and test in Europe conference and exhibition (DATE), Grenoble, France, 18–22 March 2013, pp 1259–1264
3.
Tehranipoor M, Wang C (eds) (2011) Introduction to hardware security and trust. Springer, New York, p 427
4.
Guin U, DiMase D, Tehranipoor M (2014) Counterfeit integrated circuits: detection, avoidance, and the challenges ahead. J Electr Test Theory Appl (JETTA) 30:9–23CrossRef
5.
Marques-Silva JAP, Sakallah KA (1996) GRASPVA new search algorithm for satisfiability. In: Proceedings of the ICCAD, pp 220–227
6.
Li CM, Anbulagan (1997) Heuristics based on unit propagation for satisfiability problems. In: Proceedings of IJCAI, pp 366–371
7.
Malik S, Zhao Y, Madigan CF, Zhang L, Moskewicz MW (2001) Chaff: engineering an efficient SAT solver. In Proceedings of the DAC, pp 530–535. ([62] Marques-Silva JAP, Sakallah KA (1996) GRASPVA new search algorithm for satisfiability. In: Proceedings of the ICCAD, pp 220–227)
8.
Subramanyan P, Ray S, Malik S (2015) Evaluating the security of logic encryption algorithms, HOST
9.
Goldstein LH (1979) Controllability/observability analysis of digital circuits. IEEE Trans Circuits and Syst (CAS) 26(9):685–693CrossRef
10.
Goldstein L, Thigpen E (1980) SCOAP sandia controlability/observability analysis program. In: Proceedings of the 1980 design automation conference, pp 190–196
11.
Bennetts R (1984) Design of testable logic circuits. Addison-Wesley, Reading
12.
13.
Brglez F, Pownall P, Hum R (1984, October) Applications of testability analysis: from ATPG to critical delay path tracing. In Proceedings of the 1984 international test conference on the three faces of test: design, characterization, production (ITC’84). IEEE Computer Society, Washington, DC, USA, pp 705–712
14.
Seth SC, Pan L, Agrawal VD (1985, June) PREDICT-probabilistic estimation of digital circuit testability. In: Proceedings of the fault tolerant computing symposium, pp 220–225
15.
Yang B, Wu K, Karri R (2004) Scan based side channel attack on dedicated hardware implementations of data encryption standard. In: Proceeding of the IEEE international test conference 2004 (ITC 2004), 26–28 October 2004, pp 339–344
16.
Yang B, Wu K, Karri R (2005) Secure scan: a design-for-test architecture for crypto chips. IEEE Trans Comput Aided Des Integr Circuits Syst 25(10):2287–2293CrossRef
17.
Ebrard E, Allard B, Candelier P, Waltz P (2009) Review of fuse and antifuse solutions for advanced standard CMOS technologies. Elsevier Microelectr J 40(12):1755–1765CrossRef
18.
19.
Hely D, Flottes ML, Bancel F, Rouzeyre B, Berard N, Renovell M (2004) Scan design and secure chip (secure IC testing). In: Proceedings of the 10th IEEE international on-line testing symposium, pp 219–224
20.
Lee J, Tehranipoor M, Patel C, Plusquellic J (2007) Securing designs against scan-based side-channel attacks. IEEE Trans Dependable Secure Comput 4(4):325–336CrossRef
21.
Rosenfeld K, Karri R (2010) Attacks and defenses for JTAG. IEEE Des Test Comput 27(1):36–47CrossRef
22.
Sourgen L (1993) Security locks for integrated circuit. US Patent # 5264742
23.
Busky RF, Frosik BB (2006) Protected JTAG. Proceeding of the IEEE 2006 international conference on parallel processing workshops. Columbus, OH, USA, pp 407–414
24.
Clark CJ, Riccihetti M (2004) A code-less BIST processor for embedded test and in-system configuration of boards and systems. IEEE test conference 2004:857–866
25.
Saqib F, Areno M, Aarestad J, Plusquellic J (2014) An ASIC implementation of a hardware-embedded physical unclonable function. In: IET Comput Dig Tech 8(6):288–299 (Patent Pending)
26.
27.
28.
29.
30.
Chakraborty RS, Bhunia S (2009) HARPOON: an obfuscation-based SoC design methodology for hardware protection. IEEE Trans Comput Aided Des Integr Circuits Syst (TCAD) 28(10):1493–1502CrossRef
31.
Roy J, Koushanfar F, Markov I, EPIC: ending piracy of integrated circuits. In: Proceedings of the design automation and test in Europe (DATE), pp 1069–1074
32.
Rajendran J, Pino Y, Sinanoghu O, Karri R (2012) Security analysis of logic obfuscation. ACM/ IEEE49th design automation conference (DAC), 3–7 June 2012. CA, USA, San Francisco, pp 83–89
33.
Ranjendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoghu O, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424MathSciNetCrossRef
34.
Alkabani Y, Koushanfar F (2007) Active hardware metering for intellectual property protection and security. Proceedings of 16 USENIX security symposium, (2007) USENIX Association. Berkley, CA, USA, pp 291–306
35.
Koushanfar F, Qu G (2001) Hardware metering. In: Proceedings of the IEEE design automation conference 2001 (DAC 2001), pp 490–493
36.
Liu B, Wang B (2014) Reconfiguration-based VLSI design for security. IEEE J Emerg Selected Top Circuits Syst 2014 (JETCAS 2014), 5(1):98-=108
37.
Baumgarten A, Tyag A, Zambreno J (2010) Preventing IC piracy using reconfigurable logic barriers. IEEE Des Test Comput 27(1):66–75CrossRef
38.
Rostami M, Koushanfar F, Rajendran J, Karri R (2013) Hardware security: threat models and metrics. In: Proceedings of the 2013 IEEE/ACM international conference on computer-aided design (ICCAD 2013). San Jose, CA, USA, 18–21 November 2013, pp 819–823
39.
Pappu R (2001) Physical one-way functions, PhD thesis, Massachusetts Institute of Technology
40.
Gassend B, Clarke D, Van Dijk M, Devadas S (2002) Silicon physical random functions. In: Proceedings of the 9th ACM conference on computer and communication security, 2002, pp 148–160
41.
Suh GE, Devadas S (2007) Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th ACM/IEEE design automation conference (DAC ’07). San Diego, CA, USA, 4–8 June 2007, pp 9–14
42.
Maiti A, Gunreddy V, Schaumont P (2011) A systematic method to evaluate and compare the performance of physical unclonable functions. J Int Assoc Cryptogr Res (IACR) ePrint, 657:22
43.
44.
45.
Killmann W, Schindler W (2011) A proposal for: functionality classes for random number generators. In: AIS, September 2011, p 133
46.
Su Y, Holleman J, Otis B (2007) A 1.6pJ/bit 96 percant stable chip ID generating circuit using process variations. In: Proceedings of the 2007 IEEE international solid-state circuits conferences (ISSCC), pp 200–201
47.
Kumar SS, Guajardo J, Maes R, Schrijen GJ, Tuyls P (2008) Extended abstract: the butterfly PUF protecting IP on every FPGA. In: Proceedings of the IEEE international workshop on hardware-oriented security and Trust, 2008 (HOST 2008). Anaheim, CA, USA, June 2008, pp 67–70
48.
Gassend B, Lim D, Clarke D, Van Dijk M, Devadas S (2004) Identification and authentication of integrated circuits. Concurrency Comput Pract Exper 16(11):1077–1098CrossRef
49.
Lee JW, Lim D, Gassend B, Suh GE, Dijk MV, Devadas S (2004) A technique to build a secret key in integrated circuits for identification and authentication applications. In: Digest of Technical Papers, IEEE 2004 VLSI Circuits Symposium, 17–19 June 2004, pp 176–179
50.
Lofstrom K, Daasch WR, Taylor D (2000) IC identification circuits using device mismatch. In: IEEE digest of technical papers, (2000) international solid state circuits conference. IEEE, San Francisco, CA, USA. February, 2000, pp 372–373
51.
Puntin D, Stanzione S, Iannaccone G (2008) CMOS unclonable system for secure authentication based on device variability. Conference on solid-state circuits 2008:130–133
52.
Ruhrmair U, Jaeger C, Bator M, Stutzmann M, Lugli P, Csaba G (2011) Applications of high-capacity crossbar memories in cryptography. IEEE Trans Nanotech 10(3):489–498CrossRef
53.
Ganta D, Vivekraja V, Priya K, Nazhandali L (2011) A highly stable leakage-based silicon physical unclonable functions. IEEE 2011 24th international conference on VLSI design. Chennai, India, 2–7 January 2011, pp 135–140
54.
Helinski R, Acharyya D, Plusquellic J (2009) Physical unclonable function defined using power distribution system equivalent resistance variations. In: 46th ACM/IEEE design automation conference. San Francisco, CA, USA 26–31 July 2009, pp 676–681
55.
Ismari D, Plusquellic J (2014) IP-level implementation of a resistance-based physical unclonable function. In: 2014 IEEE international symposium on hardware-oriented security and trust (HOST, 2014). Arlington, VA, USA, 6–7 May 2014, pp 64–69
56.
Chakraborty R, Lamech C, Acharyya D, Plusquellic J (2013) A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. In: IEEE 2013 50th ACM/EDAC/IEEE design automation conference (DAC, 2013). Austin, TX, USA, 29 May–7 June 2013, pp 1–10
57.
Che W, Saqib F, Plusquellic J (2015) PUF-based authentication, invited paper, international conference on computer aided design, November 2015, pp 337–344
58.
Zheng Y, Krishna AR, Bhunia S (2013) ScanPUF: robust ultralow-overhead PUF using scan chain. In: IEEE 2013 18th Asia and South Pacific design automation conference (ASP-DAC, 2013). Yokohama, Japan, 22–25 January 2013, pp 626–631
59.
Rahman T, Forte D, Fahrny J, Tehranipoor M (2014) ARO-PUF: An aging-resistant ring-oscillator PUF design. In: IEEE design, automation, and test in Europe conference, 2014 (DATE, 2014). Dresden, Germany 24–28 March 2014, pp 1–6
60.
Rührmair U, Sehnke F, Sölter J, Dror G, Devadas S, Schmidhuber J (2010) Modeling attacks on physical unclonable functions. In: Proceedings of the 17th ACM conference computer and communications security 2010 (CCS ’10), pp.237–249
61.
Rahman MT, Xiao K, Forte D, Zhang X, Shi J, Tehranipoor M (2014) TI-TRNG: technology independent true random number generator. In: 2014 51st ACM/EDAC/IEEE design automation conference (DAC 2014). San Francisco, CA, USA, June 2014, pp 1–6
62.
Wendt JB, Potkonjak M (2014) Hardware obfuscation using PUF-based logic. In: 2014 IEEE/ACM international conference on computer-aided design (ICCAD 2014). San Jose, CA, USA, 2–6 November 2014, pp 270–271
63.
Alkabani Y, Koushanfar F, Potkonjak M (2007) Remote activation of ICs for piracy prevention and digital right management. In: Proceedings of the IEEE/ATM international conference on computer-aided design (CAD), 2007. San Jose, CA, USA, 4–8 November 2007, pp 674–677
64.
Eichelberger EB, Williams TW (1977) A logic design structure for LSI testability. In: Proceedings of the design automatic conference (DAC), pp 462–468
Metadaten
Titel
VLSI Test and Hardware Security Background for Hardware Obfuscation
verfasst von
Fareena Saqib
Jim Plusquellic
Copyright-Jahr
2017
Buch
Hardware Protection through Obfuscation

Print ISBN: 978-3-319-49018-2

Electronic ISBN: 978-3-319-49019-9

Copyright-Jahr: 2017

DOI
https://doi.org/10.1007/978-3-319-49019-9_2

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