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Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.



1. Promise and Pitfalls of WSI

Wafer scale integration has had several serious trials, and each time it has failed. After each failure there has been a period of critical review; and then, like the phoenix, a new set of innovators and investors rise from the ashes to make yet another attempt. By itself, this very process is informative. Talented people do not invest their time and money in ill conceived enterprises. They believed the risks could be managed, and that the prize was worth the effort.
Joe E. Brewer

2. Feasibility of Large Area Integrated Circuits

Research in the area of wafer scale integration has been conducted with varying degrees of success since the 1960s. Unfortunately, failures in this area have been much better publicized than successes. The especially spectacular failure of Trilogy [1] is still very well remembered though much less understood. Consequently, despite the undisputable potential of WSI, large area VLSI systems are still considered to be economically justifiable for military applications and technologically feasible only if fabricated in expensive research labs. Such opinions are supported both by a few publications and by the commonly held opinion that it is very hard to achieve a working VLSI circuit with an area much larger than 1 cm2 to 2 cm2.
Wojciech Maly

3. Architectural Yield Optimization

Fabrication of integrated circuits or systems that span an entire wafer or a significant part of a wafer have held the interest of a number of semiconductor researchers [1]. The expected benefits of smaller size, increased reliability, reduced cost, shorter signal delays, and simpler packaging are significant. Unfortunately, most of the previously reported attempts have been surpassed by increased density, improved circuitry, and better packaging of conventional integrated circuits.
N. R. Strader, J. C. Harden

4. Spare Allocation/Reconfiguration for WSI

This chapter examines the issues involved in efficiently allocating spares in reconfigurable WSI architectures as a means of enhancing yield and system reliability. The focus is on spare allocation algorithms for architectures with dedicated spares and redundant interconnects. Integration of diagnosis and spare allocation is also examined. In conclusion an example computer-aided design and analysis workbench for reconfiguration algorithms and reconfigurable architectures is presented.
W. Kent Fuchs, Sy-Yen Kuo

5. A WSI Image Processor

Recent advances in VLSI parallel-processing chip architecture have now provided the enabling technology for the production of real-time, low to medium resolution image processing modules. Indeed, a number of VLSI chips, incorporating from 8 to 72 processing elements on a single Silicon die, are currently in development for the construction of SIMD image processing arrays. However, such image processing modules remain large and expensive, attracting a limited and mainly military market. Nevertheless, it is widely believed that a particularly lucrative market exists, especially in the fields of high speed graphics and industrial robotics, for smaller and lower cost real-time image processing modules.
R. M. Lea

6. The 3-D Computer: An Integrated Stack of WSI Wafers

If it could be said that a single goal has motivated the development of advanced electronic systems over the past thirty years, it would probably be the attainment of an ever higher processing capability per unit volume. From the vacuum tube through the transistor, to the microelectronic era, and through a multitude of accompanying advances in physical packaging, the drive has consistently been to increase the amount of functional capability that can be contained within a given physical envelope. In applications where limited space is a dominant design parameter, increase in compactness has been the primary motivating factor. In other circumstances, the increased processing speed, reduced power consumption, and higher reliability that accompany higher levels of integration have been the driving constraints. In virtually all instances, though, the end goal has been the same: increase the packaging density of the active electronic elements.
Michael J. Little, Jan Grinberg

7. Laser Restructurable Technology and Design

The Restructurable VLSI project at MIT Lincoln Laboratory has developed a design methodology, new technology, and CAD tools for WSI. Six wafer scale systems have been fabricated and three of much larger size are being designed. Figure 1 shows one of these packaged WS circuits. The accomplishments and current research status of this project, which was conceived in 1979 [1], are described in this chapter.
Jack Raffel, Allan H. Anderson, Glenn H. Chapman

8. High Yield In-Situ Fabrication of Multilevel Interconnections for WSI

“In-situ” fabrication refers to wafer processing in a completely controlled, ultraclean environment. Although not essential for the strict definition, this concept usually refers to a sequence of operations carried out in a single work chamber, or a series of such work chambers [1]. Figure 1 conceptually illustrates such a system which in this case is designed for Ultra High Vacuum (UHV) processing. The transfer from chamber to chamber is highly automated, and is executed through environmentally controlled ports. Hence, the in-situ process is essentially performed in a single integrated machine. Additionally, the concept embraces selection of processing steps which suppress defects to an absolute minimum, ignoring for the moment the issues of cost. This concept of suppression of defects involves addressing all sources of defects, not just particulate defects. However, the ultimate goal of in-situ processing is the elimination entirely of the use of liquids in wet processing steps, the introduction of all deposition and etching reactants as gases or vapors in ultra clean vessels, and the use of extreme chemical purity. Often this implies the use of low level or even ultra high vacuum as the background environment. Since rubbing of mechanical surfaces in manipulation fixtures and gate valves can introduce fine particles (some of which become electrostatically charged in a vacuum) even these mechanical movements must be reduced to the minimum.
J. F. McDonald, S. Dabral, H. T. Lin

9. Wafer-Scale Testing/Design for Testability

Testing is an integral part of the production and operation of computer systems, whether they are implemented in WS I or in more traditional technologies. As digital systems become more complex, they are characterized by more internal circuitry per I/O line and larger internal state spaces. This makes testing complex systems as integrated units very difficult. The testing problem can be made more tractable by partitioning them into subsystems that can be tested separately. With very complex integrated systems, this partitioning requires either design for testability, built-in self test (BIST) techniques, or both, since otherwise the entire integrated system would have to be tested through its inputs and outputs as a monolithic unit.
Donald S. Fussell, Miroslaw Malek, Sampath Rangarajan

10. Wafer-Scale Multichip Packaging Technology

With the many difficulties facing monolithic wafer-scale integration, there has been a significant amount of recent activity focusing on thin-film, multichip packaging approaches utilizing silicon wafers for the substrate. The breadth of these activities can be seen in Table 1, from Hagge [1].
R. Wayne Johnson, Richard C. Jaeger, Travis N. Blalock


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