In Chapter 4, we compute the various delays of circuits, both combinational and sequential. The delay of a circuit is commonly used as a measure for the circuit’s computational performance, i.e. how fast a circuit can compute its outputs. Thus, conventionally, input data are supplied to a circuit in intervals greater than or equal to the delay of the circuit. For example, in the pipelined combinational circuit shown in Figure 5.1 where blocks of combinational circuits are sandwiched between banks of latches, the clock period is chosen to be greater than or equal to the maximum topological delay (or the maximum true delay) of the combinational logic. At this frequency, data in any logic block have enough time to propagate through and settle before new data enter. However, in wavepipelining mode, the circuit in Figure 5.1 will be clocked at a period less than the maximum topological delay (or true delay) of a stage; thus a data wave is pumped into a stage before the previous wave reaches the registers at the end of the stage. So wavepipelining circuits operate at higher speeds than conventional circuits, sometimes orders of magnitude higher. Since the clock period is shorter than the delay of a circuit, data from neighboring clock cycles co-exist in the circuit simultaneously, and they can interact to cause the circuit to compute incorrectly. For instance, if a long path and a short path converge at a gate and the clock frequency is fast enough, then the present data on the short path can arrive at the gate earlier than the previous data on the long path, resulting in an invalid computation. Hence wavepipelining circuits involve complex signal interactions in the temporal domain and their proper operations require precise timing analysis.
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William K. C. Lam
Robert K. Brayton
- Springer US