Winning the SoC Revolution

We cover SoC design from its roots in hardware design reuse and the movements in the mid-1990’s that led to the creation of a reuse guideline-based approach for block-based design, the formation of the Virtual Socket Interface Alliance (VSIA), and the development of the block-based approach to SoC composition. We discuss the early successes and failures of IP reuse and what has been learned from these approaches. We will study the most successful SoC design methodology seen to this date: the platform-based design approach. Finally, we conclude by looking ahead to new styles of SoC and new design approaches which may emerge in the future.

SoC design incorporates the complete panoply of complex IC and embedded software design issues, including their relationships to other design tasks such as chip packaging and printed circuit board design. How one sets up one’s design methodology becomes one of the most critical factors for success. This chapter presents an overview of the breadth and scope of the design steps required for the design of an SoC. It begins with a discussion of platform based design as one of the overarching approaches to “winning” with SoCs. It then describes the basic steps- system design, embedded software design, functional verification, hardware IC design, and analog/mixed-signal in SoCs. This is followed by a discussion of some of the often forgotten other components- the infrastructure required, the interfaces between the design teams, and the “meta methods” or design management related tasks. This chapter also sets the stage for the remainder of the book often referring to later chapters for “real” design experiences and more detailed discussions.

It is not just technical challenges that confront designers of complex SoC devices. There are many organizational and management challenges as well. In this chapter we discuss structural, organizational, communications and other non-technical challenges and issues that SoC designers must face. These include the fundamental concepts of interfaces: between design groups, between hardware and software, between system designers and implementers, and between design and manufacturing. We conclude with a detailed discussion of foundry interfaces.

This chapter will outline the challenges in platform development for digital consumer home devices delivering multimedia content and novel services and applications. It will detail the requirements on this market and the approaches taken by Philips Semiconductors when developing the Nexperia-Digital Video Platform. The Nexperia-Digital Video Platform (Nexperia-DVP) comprises a family of Systems on a Chip (SoCs) and a software platform that allows Philips’ customers to build cost effective, flexible Digital Video appliances.

Platform-based design of SoC, as practiced by Texas Instruments, has two key characteristics: platforms are defined hierarchically and software plays as critical a role as hardware. We illustrate these points using the TI OMAP™ platform as an example. Development of new platform family members requires a number of system-level design processes to be carried out. Multiprocessor platforms need a particular focus on SW architectures. We conclude with a detailed description of the TI Wireless SoC platform.

System-on-a-chip (SoC) designs represent a rapidly growing segment of application-specific integrated circuit (ASIC) and application-specific standard products (ASSP) designs. The Worldwide Design Center (WWDC) in IBM Microelectronics’ ASIC organization has been designing SoCs for both internal and external customers since the mid-1990s. The experience gained over the past several years has led to methodology refinements that greatly reduced time-to-market for designs of increasing complexity. The key factors to reducing SoC time to market include standard interconnects, verification methods, the development of reusable platforms, and the enabling of concurrent software development. These factors — and the impact of the methodology on development cycles and resource requirements — will be discussed. Remaining challenges are highlighted in the conclusion.

Xilinx relies on systematic design reuse to make the benefits of system on chip integration available to the widest design community in an effective and affordable manner. Platform-based design is important in the design of FPGA architectures and is of growing significance in the design of systems incorporating FPGAs. Platform-based design with FPGAs is similar to platform based design with ASICs but noteworthy differences are also evident. The unique features of FPGAs can give rise to new types of platforms, such as the self-reconfiguring platform, that exhibit some completely novel capabilities. Design reuse is become increasingly important in the FPGA community as average design sizes continue to grow. One likely consequence of this trend is that platform-based design will proliferate and evolve further in the hands of the FPGA design community.

We are now in the era of programmable logic. The need for low-cost, high-performance methods of getting to market in the shortest amount of time are ever present. This requires tools and methodologies that leverage the strengths of the designers, utilize known-to-work components, and allow rapid experimentation and innovation. Altera’s SOPC Builder is this tool. SOPC Builder is used to construct embedded “Systems on a Programmable Chip” (SOPC) from a wide variety of components that are available natively (the Nios soft-core microprocessor, communications IP, memory interfaces, timers, etc.) or from 3rd party IP providers. Additionally it is a framework into which developers can place their own custom IP cores for easy reuse. The power of this tool and design methodology lies in the fact that it abstracts away the tedious tasks, such as developing the bus wiring, arbitration logic, and memory map decode, and allows the designer to spend more time on architectural issues, such as system performance or software/hardware co-design. With SOPC Builder the designer is able to iterate through designs quickly, testing which one will provide the most optimal performance for the given problem, testing things like simultaneous multi-master architectures, multi-processors, and where to make the split between software algorithms and hardware acceleration. Working systems are generated in minutes, and architectural evolution can begin immediately, giving faster time-to-market and providing a perfectly tailored solution in the end.

We describe the use of star-IP core-based subsystems as the cornerstone of a platform-based design paradigm. An ARM platform is an instantiation of a set of carefully market-targeted architectural-decisions encapsulated in an embedded and configurable subsystem consisting of an ARM core, AMBA™ Communications fabric and a ported operating system (OS). Around this pre-specified sub-system, a derivative-product development-package is supplied. This development package provides for configuration and extension of the platform during the creation of an optimized and differentiated system-on-chip (SoC) design. We describe the structure of this development-package, and its foundation in a set of mutually consistent model-views of the platform design. Each platform model provides the speed and visibility required for specific SoC development tasks: hardware integration and development, hardware dependent software development, application software development, and system verification and validation. In this chapter we describe both the theory of platform support, and a specific ARM instantiation of this: the ARM1136JF-S™ PrimeXsys Platform.

The productivity gap between the designer and the opportunities for silicon integration places increasing pressure on system verification in particular. A comprehensive design flow for digital systems from high-level algorithmic specifications to FPGA-based emulation and final ASIC implementation is presented. The design is entered only using a component library with predictable performance, therefore, enabling rapid system development and easing the verification burden. Hardware emulation, from this description, enables rapid prototyping of large systems where gate-level simulations are impractical. The primary goal of the emulator is to support design space exploration of real-time algorithms. The design environment is customized towards low-power and data-flow dominant architectures, particularly focusing on applications related to wireless communications. The design process of a 1 Mbit/s transmission system is explored, demonstrating the design convenience and the early performance analysis.

Advances in silicon technology have fueled much of the growth in SoC performance and density. Yet these technology advances have not come easily: each new technology generation brings with it a new set of technology related design considerations and challenges. This chapter outlines the major technology issues facing current and future SoC designers. These challenges are divided into issues that influence design, those that influence manufacture and those that relate to affordability. The design issue section outlines problems relating to performance scaling, power management, signal integrity, parametric variability and reliability. The manufacturability section describes issues relating to manufacturing yield and lithography challenges. Finally, the affordability section covers issues relating to rising engineering costs and technology trends. Each topic begins with a summary of the principal issues and trends, followed by a discussion of the associated SoC impact and mitigation strategies.