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FPGA design flows have become very similar to ASIC flow. They both usually start from RTL and require a number of similar physical and timing constraints in order to ensure proper functionality and timing on hardware. Adoption of industry standards has also helped with the convergence between the two worlds, particularly on the timing constraints side via the adoption of SDC and deprecation of proprietary equivalent formats. The main differences remain around the rules to be followed during the design implementation. ASICs come with an extensive set of manufacturability and testability rules, while FPGA designs need to follow a set of higher level rules such as device capacity and architecture features compatibility. These differences are reflected in the FPGA design flow where the tools are able to simplify or hide a number of complex rules that are typically encountered in ASIC flows, for example on signal integrity, and automatically create some constraints such as generated clocks or jitter. The following chapter will focus on how SDC support has been extended in Xilinx new generation of FPGA compilation software. The Xilinx extension to SDC is called XDC.
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- XDC: Xilinx Extensions to SDC
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- Chapter 17