Comment on “realization of series and parallel R-L and C-D impedances using single differential voltage current conveyor”

Abstract

The comment is related to the recently published paper given in [1] dealing with the implementation of series and parallel R-L and C-D impedances using a single differential voltage current conveyor (DVCC). Nevertheless, straightforward analysis of the circuit in Fig. 3(b) of [1] and also given in Fig. 1 shows that it has a problem because it makes its input voltage V _in = 0. Therefore, it can not realize parallel (–L)–(–R) simulator as claimed in [1].

Alternatively, a circuit given in Fig. 2 for realizing parallel (–L)–(–R) simulator employing a single minus-type DVCC (DVCC–) and a minimum number of passive components is proposed. The introduced circuit employs a grounded capacitor, and requires no critical component matching constraints thus it is suitable for fully integrated circuit technology. If plus-type DVCC (DVCC+) is replaced instead of the DVCC–, this proposed simulator can realize parallel (L)–(R) simulator.