- 1 J. Tang, E. S. Davidson, and J. Tong, " Polycyclic Vector Scheduling vs. Chaining on 1-Port Vector Supercomputers," in Proc. of Supercomputing '88, pp. 122-129, 19 88. Google ScholarDigital Library
- 2 J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, chapter 6.8, Morgan Kaufmann Publishers, 1990. Google ScholarDigital Library
- 3 C. Eisenbeis, W. J alby, and A. Lichnewsky, "Squeezing More CPU Performance Out of a Cray-2 by Vector Block Scheduling," in Proc. of Supercomputing '88, pp. 237-246, 1988. Google ScholarDigital Library
- 4 B. R. Rau, C. D. Glaeser, and R. L. Picard, "Efficient Code Generation for Horizontal Architectures' Compiler Techniques and Architectural Support," in Proc. of 9th Annual isca, pp. 295-304, 1982. Google ScholarDigital Library
- 5 B. R. Rau, D. W. L. Yen, W. Yen, and R. A. Towle, "The Cydra 5 Departmental Supercomputer," IEEE Computer, pp. 12-35, 1989. Google ScholarDigital Library
- 6 J. H. Patel and E. S. Davidson, "Improving the Throughput of a Pipeline by Insertion of Delays," in Proc. Third Annual I$CA, pp. 159-164, 1976. Google ScholarDigital Library
- 7 P. Y. Hsu, Highly Concurrent Scalar Processing, PhD thesis, Coordinated Science Laboratory Report #49, Univ. of Illinois, 1986. Google ScholarDigital Library
- 8 C. Eisenbeis, W. J alby, and A. Lichnewsky, "Compile-Time Optimization of Memory and Register Usage on the Cray2," in Proceedings of the Second Workshop on Languages and Compilers, Urbana llinois, August 1989. Google ScholarDigital Library
- 9 M. Lam, A Systolic Array Optimizing Compiler, PhD thesis, Carnegie Mellon University, 1987. Google ScholarDigital Library
- 10 F. H. McMahon, "The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range," Technical Report UCRL-53745, Lawrence Livermore National Laboratory, December 1986.Google Scholar
- 11 B. R. Rau, M. S. Schlansker, and D. W. L. Yen, "The Cydra 5 Stride-Insensitive Memory System," in Proc. of International Conference on Parallel Processing, pp. 1-242-246, 1989.Google Scholar
Index Terms
- Vector register design for polycyclic vector scheduling
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