Bo Zhai
Trevor Mudge
ABSTRACT
Subthreshold circuit design has become a popular approach for building energy efficient digital circuits. One drawback is performance degradation due to the exponentially reduced driving current. This had limited subthreshold circuits to relatively low performance applications such as sensor networks. To retain the excellent energy efficiency while reducing performance loss, we propose to apply subthreshold and near-threshold techniques to chip multi-processors. We show that an architecture where several slower cores are clustered together with a shared faster L1 cache is optimal for energy efficiency, because processor cores and memory operate best at different supply and threshold voltages. In particular, SPLASH2 benchmarks show about a 53% energy improvement over the traditional CMP approach (about 70% over a single core machine).
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- B. Zhai, S. Hanson, et al., "Analysis and Mitigation of Variability in Subthreshold Design", IEEE ISLPED, 2005 Google ScholarDigital Library
- B. Calhoun and A. Chandrakasan, "A 256kb Sub-threshold SRAM in 65nm CMOS", IEEE ISSCC, 2006Google ScholarCross Ref
- N. Verma, A. Chandrakasan, "A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy", IEEE ISSCC, 2007Google Scholar
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Index Terms
- Energy efficient near-threshold chip multi-processing
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