Abstract
Cosimulation strategies allow us to simulate and verify HW/SW embedded systems before the real platform is available. In this field, there is a large variety of approaches that rely on different communication mechanisms to implement an efficient interface between the SW and the HW simulators. However, the literature lacks a comprehensive methodology which addresses the need for integrating and synchronizing heterogeneous simulators, like, for example, the SystemC simulation kernel for HW modules and an instruction set simulator for SW applications, without being intrusive for the HW and SW descriptions involved in the simulation. In this context, this article presents, compares, and integrates in a system-level framework two different co-simulation strategies for modeling, analyzing, and validating the performance of a HW/SW embedded system. Moreover, for both of them, a mechanism is proposed to provide an accurate time synchronization of the HW/SW communication. The first strategy is intended to provide an early cosimulation environment where HW/SW interaction can be validated without involving the operating system. The communication is implemented between a single SW task and a SystemC description of an HW module by exploiting the features of the remote debugging interface of a debugger (the GNU GDB), and by modifying the SystemC simulation kernel. On the other hand, the second strategy is intended to be used in further development steps, when the operating system is introduced to validate the cosimulation between HW modules and multitasking SW applications. In this approach, the communication is implemented via interrupts by using the features offered by the operating system.
Experimental results are reported on two different case studies to analyze and compare the effectiveness of both the approaches.
- Bacivarov, I., Yoo, S., and Jerraya, A. 2002. Timed HW-SW cosimulation using native execution of OS and application SW. In Proceedings of IEEE International High-Level Design Validation and Test Workshop. 51--56. Google ScholarDigital Library
- Balarin, F., Chiodo, M., Giusto, P., Hsieh, H., Jurecska, A., Lavagno, L., Passerone, C., Sangiovanni-Vincentelli, A., Sentovich, E., Suzuki, K., and Tabbara, B. 1997. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer, Amsterdam. Google ScholarDigital Library
- Benini, L., Bertozzi, D., Bruni, D., Drago, N., Fummi, F., and Poncino, M. 2003. Systemc cosimulation and emulation of multi-processor SoC designs. IEEE Computer 36, 4, 53--59. Google ScholarDigital Library
- Buck, J., Ha, S., Lee, E., and Messerschmitt, D. 1994. Ptolemy: A framework for simulating and prototyping heterogeneous systems. Int. J. Comput. Simulation 4, 2, 155--182.Google Scholar
- Coste, P., Hessel, F., Marrec, P. L., Sugar, Z., Romdhani, M., Suescun, R., Zergainoh, N., and Jerraya, A. 1999. Multilanguage design of heterogeneous systems. In Proceedings of IEEE International Workshop on Hardware-Software Codesign. 54--58. Google ScholarDigital Library
- De Micheli, D., Ernst, R., and Wolf, W. Eds. 2001. Readings in Hardware/Software Co-design, Morgan Kaufmann, 2001 Google ScholarDigital Library
- Drótos, D. μCSim: Software Simulator for Microcontrollers. http://mazsola.iit.uni-miskolc. hu/˜drdani/embedded/s51/.Google Scholar
- eCos. http://sources.redhat.com/ecos/.Google Scholar
- Fummi, F., Martini, S., Perbellini, G., and Poncino, M. 2004. Native ISS-SystemC integration for the cosimulation of multi-processors SoC. In Proceedings of the IEEE Conference on Design Automation and Test in Europe. 564--569. Google ScholarDigital Library
- Ghosh, A., Bershteyn, M., Casley, R., Chien, C., Lipsie, A. J. M., Tarrodaychik, D., and Yamamoto, O. 1995. A hardware-software co-simulator for embedded system design and debugging. In Proceedings of IEEE Asian and South Pacific Design Automation Conference. 155--164. Google ScholarDigital Library
- Gnu project web server. http://www.gnu.org/software/.Google Scholar
- Kim, D., Rhee, C.-E., Yi, Y., Kim, S., Jung, H., and Ha, S. 2002. Virtual synchronization for fast distributed cosimulation of dataflow task graphs. In Proceedings of the IEEE International Symposium on System Synthesis. 174--179. Google ScholarDigital Library
- Lahiri, K., Raghunathan, A., Lakshminarayana, G., and Dey, S. 2000. Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips. In Proceedings of ACM/IEEE Design Automation Conference. 513--518. Google ScholarDigital Library
- Liem, C., Nacabal, F., Valderrama, C., Paulin, P., and Jerraya, A. 1997. System-on-chip cosimulation and compilation. IEEE Design and Test of Comput. 14, 2, 16--25. Google ScholarDigital Library
- Liu, J., Lajolo, M., and Sangiovanni-Vincentelli, A. 1998. Software timing analysis using HW/SW cosimulation and instruction set simulator. In Proceedings of the IEEE International Workshop on Hardware/Software Co-design. 65--69. Google ScholarDigital Library
- Mentor Graphics Inc. http://www.mentor.com/seamless.Google Scholar
- Microelectronics, S. LIS3LV02DQ MEMS Inertial sensor. Rev. 1.0.Google Scholar
- Moussa, I., Grellier, T., and Nguyen, G. 2003. Exploring SW performance using SoC transaction-level modelling. In Proceedings of the IEEE Conference on Design Automation and Test in Europe. 120--125. Google ScholarDigital Library
- Muhr, H., Holler, R., and Horauer, M. 2006. A heterogeneous hardware-software cosimulation environment using user mode linux and clock suppression. In Proceedings of the 2nd IEEE/ASME International Conference. 1--6.Google Scholar
- Patel, H., Mathaikutty, D., Berner, D., and Shukla, S. 2006. CARH: Service-oriented architecture for validating system-level designs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 8, 1458--1474. Google ScholarDigital Library
- Psim User Guide and Reference Manual. http://sources.redhat.com/psim/manual/.Google Scholar
- Semeria, L. and Ghosh, A. 2000. Methodology for hardware/software co-verification in C/C++. In Proceedings of IEEE Asian and South Pacific Design Automation Conference. 405--408. Google ScholarDigital Library
- Sung, W. and Ha, S. 1998. Optimized timed hardware software cosimulation without roll-back. In Proceedings of the IEEE conference on Design Automation and Test in Europe. 945--946. Google ScholarDigital Library
- Synopsys Inc. http://www.synopsys.com/products.Google Scholar
- Ultimodule. http://www.ultimodule.com.Google Scholar
- Valderrama, C., Nacabal, F., Paulin, P., and Jerraya, A. 1998. Automatic VHDL-C interface generation for distributed cosimulation: Application to large design examples. Design Autom. Embed. Syst. 3, 2/3, 199--217.Google Scholar
- Yi, Y., Kim, D., and Ha, S. 2003. Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation. In Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 1--6. Google ScholarDigital Library
- Yoo, S., Bacivarov, I., Bouchhima, A., Paviot, Y., and Jerraya, A. 2003. Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer. In Proceedings of the IEEE Conference on Design Automation and Test in Europe. 550--555. Google ScholarDigital Library
- Yoo, S. and Choi, K. 1997. Optimistic timed HW-SW cosimulation. In Proceedings of the Asia-Pacific Conference on Hardware Description Language. 39--42.Google Scholar
- Yoo, S., Nicolescu, G., Gauthier, L., and Jerraya, A. 2001. Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication. In Proceedings of IEEE International Workshop on High Level Design Validation and Test. 79--82. Google ScholarDigital Library
Index Terms
- A cosimulation methodology for HW/SW validation and performance estimation
Recommendations
A unified HW/SW interface model to remove discontinuities between HW and SW design
EMSOFT '05: Proceedings of the 5th ACM international conference on Embedded softwareOne major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model HW/SW interface twice. Using two separate models introduces a ...
Gesture recognition using neural networks based on HW/SW cosimulation platform
Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate ...
Domain-Specific Language for HW/SW Co-design for FPGAs
DSL '09: Proceedings of the IFIP TC 2 Working Conference on Domain-Specific LanguagesThis article describes FSMLanguage, a domain-specific language for HW/SW co-design targeting platform FPGAs. Modern platform FPGAs provide a wealth of configurable logic in addition to embedded processors, distributed RAM blocks, and DSP slices in order ...
Comments