ABSTRACT
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed architecture, implemented in a 65nm FPGA system, consists of a pipelined interpolating time-to-digital converter (TDC). The TDC comprises a coarse time discriminator and a fine delay line, capable of sustained operation at a clock frequency of 300MHz. A Turbo version of the circuit implements a pipelined interpolating TDC with suppressed dead time to reach a conversion rate of 300MS/s at the expense of a systematic asymmetry that requires fast error correction. The TDCs proposed in this paper can be compensated for process, voltage, and temperature (PVT) variations using a conventional charge pump based feedback or a digital calibration technique. Results demonstrate the suitability of the approach for a variety of applications involving high-precision ultra-fast time discrimination, such as optical lifetime sensing, time-of-flight cameras, high throughput comlinks, RADARs, etc.
- B.K. Swann, B.J. Blalock, L.G. Clonts, D.M. Binkley, J.M. Rochelle, E. Breeding, and K.M. Baldwin. A 100-ps time-resolution cmos time-to-digital converter for positron emission tomography imaging applications. Solid-State Circuits, IEEE Journal of, 39(11):1839--1852, Nov. 2004.Google Scholar
- K. Karadamoglou, N.P. Paschalidis, E. Sarris, N. Stamatopoulos, G. Kottaras, and V. Paschalidis. An 11-bit high-resolution and adjustable-range cmos time-to-digital converter for space science instruments. Solid-State Circuits, IEEE Journal of, 39(1):214--222, Jan. 2004.Google Scholar
- H. Matsumoto, O. Sasaki, K. Anraku, and M. Nozaki. Low power high resolution tdc with fast data conversion for balloon-borne experiments. Nuclear Science, IEEE Transactions on, 43(4):2195--2198, Aug 1996.Google Scholar
- K. Maatta and J. Kostamovaara. A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications. Instrumentation and Measurement, IEEE Transactions on, 47(2):521--536, Apr 1998.Google Scholar
- F. Bigongiari, R. Roncella, R. Saletti, and P. Terreni. A 250-ps time-resolution cmos multihit time-to-digital converter for nuclear physics experiments. Nuclear Science, IEEE Transactions on, 46(2):73--77, Apr 1999.Google Scholar
- W. M. Henebry and A. Rasiel. Design features of a start-stop time-to-amplitude converter. Nuclear Science, IEEE Transactions on, 13(2):64--68, April 1966.Google Scholar
- J. Kalisz, R. Szplet, J. Pasierbinski, and A. Poniecki. Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution. Instrumentation and Measurement, IEEE Transactions on, 46(1):51--55, Feb 1997.Google Scholar
- R. Szplet, J. Kalisz, and R. Szymanowski. Interpolating time counter with 100 ps resolution on a single fpga device. Instrumentation and Measurement, IEEE Transactions on, 49(4):879--883, Aug 2000.Google Scholar
- Jian Song, Qi An, and Shubin Liu. A high-resolution time-to-digital converter implemented in field--programmable-gate-arrays. Nuclear Science, IEEE Transactions on, 53(1):236--241, Feb. 2006.Google Scholar
- C. Niclass, C. Favi, T. Kluter, M. Gersbach, and E. Charbon. A 128x128 single--photon imager with on-chip column-level 10b time-to-digital converter array capable of 97ps resolution. Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pages 44--594, Feb. 2008.Google ScholarCross Ref
- A. Rochas. Single Photon Avalanche Diodes in CMOS Technology. PhD thesis, EPF-Lausanne, Switzerland, 2003.Google Scholar
- C. Favi and E. Charbon. Techniques for fully integrated intra-/inter-chip optical communication. Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, pages 343--344, June 2008. Google ScholarDigital Library
- Barton R D and King M E. Two vernier time-interval digitizers. Nucl. Instrum. Methods, 97(359--70), 1971.Google Scholar
- Barton R G. The vernier time-measuring technique. In IRE, pages 21--30, 1957.Google Scholar
- Hoppe D R. Time interpolator. US Patent, (4,439,046), 1982.Google Scholar
- Hoppe D R. Differential time interpolator. US Patent, (4,433,919), 1982.Google Scholar
- M.J. Loinaz and B.A. Wooley. A cmos multichannel ic for pulse timing measurements with 1-mv sensitivity. Solid-State Circuits, IEEE Journal of, 30(12):1339--1349, Dec 1995.Google Scholar
- Y. Arai and T. Ohsugi. Tmc-a cmos time to digital converter vlsi. Nuclear Science, IEEE Transactions on, 36(1):528--531, Feb 1989.Google Scholar
- M.S. Andaloussi, M. Boukadoum, and E.M. Aboulhamid. A novel time-to-digital converter with 150 ps time resolution and 2.5 ns pulse-pair resolution. Microelectronics, The 14th International Conference on 2002 -- ICM, pages 123--126, Dec. 2002.Google Scholar
- Jinyuan Wu, Zonghan Shi, and I.Y. Wang. Firmware-only implementation of time-to-digital converter (tdc) in field-programmable gate array (fpga). Nuclear Science Symposium Conference Record, 2003 IEEE, 1:177--181 Vol.1, Oct. 2003.Google Scholar
- M. Mota and J. Christiansen. A high-resolution time interpolator based on a delay locked loop and an rc delay line. Solid-State Circuits, IEEE Journal of, 34(10):1360--1366, Oct 1999.Google Scholar
- http://www.mics.org/.Google Scholar
- http://www.xilinx.com/univ/.Google Scholar
Index Terms
- A 17ps time-to-digital converter implemented in 65nm FPGA technology
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