Hao Yu
Skip Abstract Section
Abstract
The existing work on via allocation in 3D ICs ignores power/ground vias' ability to simultaneously reduce voltage bounce and remove heat. This article develops the first in-depth study on the allocation of power/ground vias in 3D ICs with simultaneous consideration of power and thermal integrity. By identifying principal ports and parameters, effective electrical and thermal macromodels are employed to provide dynamic power and thermal integrity as well as sensitivity with respect to via density. With the use of sensitivity, an efficient via allocation simultaneously driven by power and thermal integrity is developed. Experiments show that, compared to sequential power and thermal optimization using static integrity, sequential optimization using the dynamic integrity reduces nonsignal vias by up to 18%, and simultaneous optimization using dynamic integrity further reduces nonsignal vias by up to 45.5%.
- Alpert, C., Kahng, A., and Yao, S. 1999. Spectral partitioning with multiple eigenvectors. Discrete Appl. Math. Google Scholar
Digital Library
- Antoulas, A., Sorensen, D., and Gugercin, S. 2001. A survey of model reduction methods for large scale systems. Contemporary Math. 193--219.Google Scholar
- Astrid, P., Weiland, S., and Willcox, K. 2007. Missing point estimation in models described by proper orthogonal decomposition. IEEE Trans. Autom. Control.Google Scholar
- Banerjee, K., Souri, S. J., Kapur, P., and Saraswat, K. C. 2001. 3D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration. Proc. IEEE, 602--633.Google Scholar
- Box, G., Jenkins, G., and Reinsel, G. 1994. Time Series Analysis: Forecasting and Control. Prentice Hall, New York. Google ScholarDigital Library
- Chiang, T.-Y., Banerjee, K., and Saraswat, K. C. ICCAD. 2001. Compact modeling and spice-based simulation for electrothermal analysis of multilevel ulsi interconnects. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Cong, J., Wei, J., and Zhang, Y. 2004. A thermal-driven floorplanning algorithm for 3d ics. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Cong, J. and Zhang., Y. 2005. Thermal via planning for 3D ICs. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Das, S. 2004. Design automation and analysis of three dimentional integrated circuits Ph. D thesis, Massachusetts Institute of Technology.Google Scholar
- Davis, W., Wilson, J., Mick, S., Xu, J., Hua, H., et al. 2005. Demystifying 3D ICs: the pros and cons of going vertical. IEEE Design and Test of Computers, 498--510. Google ScholarDigital Library
- Ding, C. and Zha, H. 2008. Spectral Clustering, Ordering and Ranking -Statistical Learning with Matrix Factorizations. Springer. Google ScholarDigital Library
- Grimme, E. J. 1997. Krylov projection methods for model reduction Ph. D thesis, University of Illinois at Urbana-Champaign.Google Scholar
- Feldmann, P. and Liu, F. 2004. Sparse and efficient reduced order modeling of linear sub-circuits with large number of terminals. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Goplen, B. and Sapatnekar, S. 2003. Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Goplen, B. and Sapatnekar, S. 2005. Thermal via placement in 3D ICs. In Proceedings of the International Symposium on Physical Design. Google ScholarDigital Library
- Hong, Y., Lee, H., Choi, J.-H., Yoo, M.-H., and Kong, J.-T. 2005. Analysis for complex power distribution networks considering densely populated vias. In Proceedings of the International Symposium on Quality Electronics and Design. Google ScholarDigital Library
- Kannan, R., Vempala, S., and Vetta, A. 2004. On clusterings: Good, bad and spectral. J. ACM. Google ScholarDigital Library
- Knickerbocker, J. U., Andry, P. S., Buchwaler, L. P., Deutsch, A., Horton, R. R., et al. 2005. Development of next-generation system-on-package technology based on silicon carriers with fine-pitch chip interconnection. IBM Res. J. (Power and Packaging), 725--754. Google ScholarDigital Library
- Li, H., Qi, Z., Tan, S., Wu, L., Cai, Y., and Hong, X. 2005a. Partitioning-Based approach to fast on-chip decap budgeting and minimization. In Proceedings of the Design Automation Conference. Google ScholarDigital Library
- Li, P., Pileggi, L., Asheghi, M., and Chandra, R. 2004. Efficient full-chip thermal modeling and analysis. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Li, P. and Shi, W. 2006. Model order reduction of linear networks with massive ports via frequency-dependent port packing. In Proceedings of the Design Automation Conference. Google ScholarDigital Library
- Li, X., Li, P., and Pileggi, L. Li. 2005b. Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Li, Z., Hong, X., Zhou, Q., Yang, H., V. Pitchumani, and Cheng, C. 2006. Integrating dynamic thermal via planning with 3D floorplanning algorithm. In Proceedings of the International Symposium on Physical Design. Google ScholarDigital Library
- Liao, W., He, L., and Lepak, K. 2005. Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 1042--1053. Google ScholarDigital Library
- Lim, S. 2005. Physical design for 3D system-on-package: Challenges and opportunities. IEEE Des. Test Comput. 532--539. Google ScholarDigital Library
- Liu, P., Tan, S. X.-D., Kong, J., McGaughy, B., and He, L. 2005. Efficient method for terminal reduction of interconnect circuits considering delay variations. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Moore, B. 1981. Principal component analysis in linear systems: Controllability, observability, and model reduction. IEEE Trans. Autom. Control, 17--32.Google ScholarCross Ref
- Odabasioglu, A., Celik, M., and Pileggi, L. 1998. PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst., 645--654. Google ScholarDigital Library
- Rathinam, M. and Petzold, L. 2003. A new look at proper orthogonal decomposition. SIAM J. Numer. Anal. 1893--1925. Google ScholarDigital Library
- Ruehli, A. E. 1974. Equivalent circuits models for three dimensional multiconductor systems. IEEE Trans. Microwave Theory Techniq. 216--220.Google ScholarCross Ref
- Ryu, C., Chung, D., Lee, J., Lee, K., Oh, J., et. al. 2005. High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3D chip stacking package. In Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging (EPEP).Google Scholar
- Sapatnekar, S. 2006. Physical design automation challenges for 3D ICs. In International Conference on IC Design and Technology.Google Scholar
- Su, H., K. Gala, and Sapatnekar, S. 2003. Analysis and optimization of structured power/ground networks. IEEE Trans. Comput.-Aid. Des. Integrated Circ. Syst. 1533--1544. Google ScholarDigital Library
- Teng, C. C., Cheng, Y. K., Rosenbaum, E., and Kang, S. M. 1997. iTEM: A temperature-dependent electromigration reliability diagnosis tool. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 882--893. Google ScholarDigital Library
- Tiwari, V., Singh, D., Rajgopal, S., Mehta, G., Patel, R., and Baez, F. 1998. Reducing power in high-performance microprocessors. In Proceedings of the Design Automation Conference. Google ScholarDigital Library
- Wang, T. and Chen, C. 2003. Thermal-ADI: A linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. IEEE Trans. Very Large Scale Integration (VLSI) Syst., 691--700. Google ScholarDigital Library
- Yu, H., Chu, C., and He, L. 2007. Off-Chip decoupling capacitor allocation for chip package co-design. In Proceedings of the Design Automation Conference. Google ScholarDigital Library
- Yu, H., He, L., and Tan, S. BMAS-. 2005. Block structure preserving model reduction. In IEEE International Workshop on Behavioral Modeling and Simulation (BMAS).Google Scholar
- Yu, H., Ho, J., and He, L. 2006a. Simultaneous power and thermal integrity driven via stapling in 3D ICs. In Proceedings of the International Conference on Computer Aided Design. Google ScholarDigital Library
- Yu, H., Shi, Y., and He, L. 2006b. Fast analysis of structured power grid by triangularization based structure preserving model order reduction. In Proceedings of the Design Automation Conference. Google ScholarDigital Library
- Yu, H., Shi, Y., He, L., and Karnik, T. 2006c. Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. In International Symposium on Low Power Electronics and Design (ISLPED). Google ScholarDigital Library
- Zhan, Y. and Sapatnekar, S. S. 2007. High efficiency green function-based thermal simulation algorithms. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. Google ScholarDigital Library
- Zhao, J., Zhang, J., and Fang, J. 1998. Effects of power/ground via distribution on the power/ground performance of C4/BGA packages. In Proceedings of the Conference on IEEE Electrical Performance of Electronic Packaging (EPEP).Google Scholar
- Zhao, M., Panda, R., and et. al. 2002a. Hierarchical analysis of power distribution networks. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst., 159--168. Google ScholarDigital Library
- Zhao, S., Roy, K., and Koh, C. 2002b. Decoupling capacitance allocation and its application to power supply noise aware floorplanning. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 81--92. Google ScholarDigital Library
- Zheng, H., Krauter, B., and Pileggi, L. 2003. On-Package decoupling optimization with package macromodels. In Proceedings of the IEEE Custom Integrated Circuits Conference.Google Scholar
Index Terms
- Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
Recommendations
Thermal and Power Integrity Based Power/Ground Networks Optimization
DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects on transistor and interconnect performance are well-studied, the ...
Simultaneous power and thermal integrity driven via stapling in 3D ICs
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided designThe existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven ...
Co-design of signal, power, and thermal distribution networks for 3D ICs
DATE '09: Proceedings of the Conference on Design, Automation and Test in EuropeHeat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solution to dramatically reduce the operating temperature of 3D ICs. In addition, ...
Comments