skip to main content
10.1145/1739025.1739037acmconferencesArticle/Chapter ViewAbstractPublication PagesasplosConference Proceedingsconference-collections
research-article

From lock to correct and efficient software transactional memory

Published:13 March 2010Publication History

ABSTRACT

Transactional memory solves many problems in lock-based parallel programs. Unfortunately, the semantics of transactions are different from those of critical sections defined by locks. The semantic differences make it difficult to correctly port existing lock-based programs to transaction-based programs. Experienced programmers accustomed to lock-based programming can easily make mistakes in transaction-based programming as parallel programs running correctly using locks can run incorrectly when converted to using transactions. This problem becomes even more severe in the efficient software transactional memory implementing weak isolation, optimistic read concurrency management and eager version management.

In this paper, we first identify three necessary properties in a program for the program execution using transactions to be equivalent to the program execution using locks. Assuming that the input lock-based program satisfies the necessary properties (i.e. well-behaved parallel programs), we next present a correctness condition for the program execution using transactions to be equivalent to the program execution using locks. Finally, we develop a correct and efficient software transactional memory implementation that satisfies the correctness condition so that locks in the well behaved parallel programs can be converted to use efficient software transactional memory easily and correctly.

References

  1. Wang, C., Chen, W., Wu, Y., Saha, B. and Adl-Tabatabai, A. Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. CGO 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Adl-Tabatabai, A., Lewis, B. T., Menon, V. S., Murphy, B. M., Saha, B., Shpeisman, T. Compiler and runtime support for efficient software transactional memory. PLDI 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Ananian, C. S., Asanovic, K., Kuszmaul, B. C., Leiserson, C. E., Lie, S. Unbounded Transactional Memory. HPCA 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Dice, Dave, Ori Shalev, Nir Shavit, Transactional Locking II, 20th International Symposium on Distributed Computing (DISC 06), Stockholm, Sweden, September 18--20, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Hammond, L., Carlstrorm, B. D., Wong, V., Hertzberg, B., Chen, M., Kozyrakis, C., and Olukotun, K. Transactional coherence and consistency. ASPLOS 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Harris, T., Plesko, M., Shinnar, A., and Tarditi, D. Optimizing Memory Transactions. PLDI 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Harris, T. L. and Fraser, K. Language support for lightweight transactions. OOPSLA 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Harris, T. L., Marlow, S., Peyton Jones, S., Herlihy, M. Composable memory transactions. PPoPP 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Herlihy, M. and Moss, J. E. B. Transactional memory: architectural support for lock-free data structures. ISCA 1993 Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Herlihy, M., Luchango, V., Moir, M., Scherer III, W. M. Software transactional memory for dynamic sized data structures. PODC 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Hudson, R. L., Saha, B. Adl-Tabatabai, A., and Hertzberg, B. C., McRT-Malloc - A Scalable Transactional Memory Allocator, ISMM '06. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Kumar, S., Chu, M., Hughes, C., Kundu, P., Nguyen, A. Hybrid transactional memory. PPoPP 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. McDonald, A., Kozyrakis, C., Olukotun, K. Architectural Semantics for Practical Transactional Memory, ISCA 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Moir, M. Hybrid Transactional Memory. Sun Microsystems Technical Report.Google ScholarGoogle Scholar
  15. Moore, K. E., Bobba, J., Moravan, M. J., Hill, M. D., Wood, D. A. LogTM: Log-based Transactional Memory. HPCA-12, 2006.Google ScholarGoogle ScholarCross RefCross Ref
  16. Rajwar, R., Herlihy, M., and Lai, K. Virtualizing transactional memory. ISCA 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Riegel, T., P. Felber, and C. Fetzer, A Lazy Snapshot Algorithm with Eager Validation, 20th International Symposium on Distributed Computing (DISC 06), Stockholm, Sweden, September 18--20, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Saha, B., Adl-Tabatabai, A., Hudson, R., Minh, C., Hertzberg, B. McRT-STM: A high performance software transactional memory system for a multi-core runtime. PPoPP 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Shavit, N., and Touitou, D. Software transactional memory. PODC 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Shriraman, A., Marathe, V. J., Dwarkadas, S., Scott, M. L., Eisnstat, D., Heriot, C., Scherer III, W. N., Spear, M. F. Hardware acceleration of software transactional memory. Techical report 887, Computer Science Department, University of Rochester, 2006.Google ScholarGoogle Scholar
  21. Wang, C., Ying, V., Wu, Y., Dynamic Binary Translation and Optimization of Legacy Library Code in a STM Compilation Environment, CC2008.Google ScholarGoogle Scholar
  22. Blundell, C., Levwis, E. C., and Martin, M. M. K. Deconstructing Transactions: The Subtleties of Atomicity. WDDD 2005.Google ScholarGoogle Scholar
  23. Banerjee, U., Bliss, B., Ma, Z., Petersen, P. Unraveling Data Race Detection in the Intel® Tread Checker. STMCS 2006Google ScholarGoogle Scholar
  24. Shpeisman, T., Menon, V., Adl-Tabatabai, A., Balensiefer, S., Grossman, D., Hudson, R. L., Moore, K. F., and Saha, B. 2007. Enforcing isolation and ordering in STM. SIGPLAN Not. 42, 6 (Jun. 2007). Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Menno, V., Balensiefer, S., Shpeisman, T., Adl-Tabatabai, A., Hudson, Saha, B., and Welc, A., Single Global Lock Semantics in a Weekly Atomic STM, TRANSACT 2008Google ScholarGoogle Scholar

Index Terms

  1. From lock to correct and efficient software transactional memory

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      INTERACT-14: Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
      March 2010
      83 pages
      ISBN:9781605589213
      DOI:10.1145/1739025

      Copyright © 2010 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 13 March 2010

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
    • Article Metrics

      • Downloads (Last 12 months)2
      • Downloads (Last 6 weeks)1

      Other Metrics

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader