Stan Liao
- 1.A. Aho, R. Sethi, and J. Ullman. Compilers Principles, Techniques and Tools. Addison-Wesley, 1986. Google Scholar
Digital Library
- 2.W-K. Cheng and Y-L. Lin. Code Generation for a DSP Processor. In Proceedings of the Int' l Symposium on High-Level Synthesis, pages 82-87, May 1994. Google ScholarDigital Library
- 3.T.H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. MIT Press, Cambridge, MA, 1990. Google ScholarDigital Library
- 4.John R. Ellis. A Compiler for VLIW Architectures. MIT Press, 1985. Google ScholarDigital Library
- 5.J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trnsactions on Computers, C- 30(7):478-490, 1981.Google ScholarDigital Library
- 6.J.G. Ganssle. The Art of Programming Embedded Systems. San Diego, CA: Academic Press, Inc., 1992. Google ScholarDigital Library
- 7.Texas Instruments. TMS320C2x User's Guide. Texas Instruments, January 1993. Revision C.Google Scholar
- 8.S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang. Storage Assignment to Decrease Code Size. In Proceedings of ACM SIGPLAN'95 Conference on Programming Language Design and Implementation, June 1995. Google ScholarDigital Library
- 9.E Marwedel and G. Goossens, editors. Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995. Proceedings of the 1994 Dagstuhl Workshop on Code Generation for Embedded Processors.Google Scholar
- 10.S. S. Pinter. Register Allocation with Instruction Scheduling: a New Approach. In Proceedings of the ACM Programming Language Design and Implementation Conference, pages 248- 257, June 1993. Google ScholarDigital Library
- 11.V. Zivojnovi6, J. Martfnez Velarde, and C. Schl~iger. DSPstone: A DSP-oriented Benchmarking Methodology. Technical report, Aachen University of Technology, August 1994.Google Scholar
Index Terms
- Code optimization techniques for embedded DSP microprocessors
Recommendations
Code Optimization Techniques in Embedded DSP Microprocessors
We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation methods typically result in inefficient code. In this ...
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)
For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a “dual instruction set”, where processor architectures support a normal (usually 32-bit) Instruction Set, and a ...
Instruction selection using binate covering for code size optimization
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided designWe address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation methods typically result in inefficient code. Instruction selection ...
Comments