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Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers

Published:23 April 1995Publication History
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References

  1. 1.IBM PowerPC 403GA 32-Bit RISC Embedded Controller data sheet Document No.MPR403DSU-01 09.02.94Google ScholarGoogle Scholar
  2. 2.CMOS5L Design Manual, IBM Engineering Specification 02G1508Google ScholarGoogle Scholar
  3. 3.A.RChandrakasan,S.Sheng and R.W.Brodersen, "Low- Power CMOS Design," in IEEE Journal of Solid State Circuits, Vol. 27, NO. 4, April 1992, pg.475Google ScholarGoogle ScholarCross RefCross Ref
  4. 4.E.B.Eichelberger and T.W.Williams, "A logic design structure for LSI testability," in Proc. 14th Design Automation Conf., June 1977, pp. 462-468 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.Anthony Correale, Jr., "Power Reduction Technique for Chips Using Common I/O'", in IBM Technical Disclosure Bulletin, Vol. 37, No. 01, January 1994Google ScholarGoogle Scholar
  6. 6.Anthony Correale, Jr., "Design considerations of a static LSSD polarity hold latch pair", in IBM Journal of Research and Development, Vol.28, No. 4, July 1984, pp.370-377Google ScholarGoogle ScholarCross RefCross Ref

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  1. Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers

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            cover image ACM Conferences
            ISLPED '95: Proceedings of the 1995 international symposium on Low power design
            April 1995
            233 pages
            ISBN:0897917448
            DOI:10.1145/224081

            Copyright © 1995 ACM

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            Publication History

            • Published: 23 April 1995

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