skip to main content
research-article

Phase-change memory: An architectural perspective

Published:03 July 2013Publication History
Skip Abstract Section

Abstract

This article surveys the current state of phase-change memory (PCM) as a nonvolatile memory technology set to replace flash and DRAM in modern computerized systems. It has been researched and developed in the last decade, with researchers providing better architectural designs which address the technology's main challenges—its limited write endurance, potential long latency, high energy writes, power dissipation, and some concerns for memory privacy. Some physical properties of the technology are also discussed, providing a basis for architectural discussions. Also briefly shown are other architectural alternatives, such as FeRAM and MRAM. The designs surveyed in this article include read before write, wear leveling, write cancellation, write pausing, some encryption schemes, and buffer organizations. These allow PCM to stand on its own as a replacement for DRAM as main memory. Designs for hybrid memory systems with both PCM and DRAM are also shown and some designs for SSDs incorporating PCM.

References

  1. Atwood, G. 2010. The evolution of phase-change memory. Micron's Innovations Blog, http://www.micronblogs.com/2010/08/what's-the-future-for-pcm/.Google ScholarGoogle Scholar
  2. Bedeschi, F., Fackenthal, R., Resta, C., Donze, E., Jagasivamani, M., Buda, E., Pellizzer, F., Chow, D., Cabrini, A., Calvi, G., Faravelli, R., Fantini, A., Torelli, G., Mills, D., Gastaldi, R., and Casagrande, G. 2009. A bipolar-selected phase change memory featuring multi-level cell storage. IEEE J. Solid-State Circuits 44, 1, 217--227.Google ScholarGoogle ScholarCross RefCross Ref
  3. Bez, R., Bossi, S., Gleixner, B., Pellizzer, F., Pirovano, A., Servalli, G., and Tosi, M. 2010. Phase change memory development trends. In Proceedings of the IEEE International Memory Workshop (IMW'10). 1--4.Google ScholarGoogle Scholar
  4. Boboila, S. and Desnoyers, P. 2010. Write endurance in flash drives: Measurements and analysis. In Proceedings of the 8th USENIX Conference on File and Storage Technologies (FAST'10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Burr, G. W., Breitwisch, M. J., Franceschini, M., Garetto, D., Gopalakrishnan, K., Jackson, B., Kurdi, B., Lam, C., Lastras, L. A., Padilla, A., Rajendran, B., Raoux, S., and Shenoy, R. S. 2010. Phase change memory technology. J. Vacuum Sci. Technol. B: Microelectronics and Nanometer Structures 28, 2, 223--262.Google ScholarGoogle ScholarCross RefCross Ref
  6. Cho, S. and Lee, H. 2009. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'09). 347--357. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Coburn, J., Caulfield, A. M., Akel, A., Grupp, L. M., Gupta, R. K., Jhala, R., and Swanson, S. 2011. NV-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'11). 105--118. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Condit, J., Nightingale, E. B., Frost, C., Ipek, E., Lee, B., Burger, D., and Coetzee, D. 2009. Better I/O through byte-addressable, persistent memory. In Proceedings of the ACM Symposium on Operating Systems Principles (SoSP'10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Dhiman, G., Ayoub, R., and Rosing, T. 2009. PDRAM: A hybrid PRAM and DRAM main memory system. In Proceedings of the 46th Annual Design Automation Conference (DAC'09). 664--469. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Dong, X. and Xie, Y. 2011. AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. In Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASPDAC'11). 31--36. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Dong, X., Xie, Y., Muralimanohar, N., and Jouppi, N. P. 2011. Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Architect. Code Optim, 8, 6:1--6:29. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Freitas, R. F. and Wilcke, W. W. 2008. Storage-class memory: The next storage system technology. IBM J. Res. Develop. 52, 439--447. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Guo, X., Ipek, E., and Soyata, T. 2010. Resistive computation: Avoiding the power wall with low-leakage, STT-MRAM based computing. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10). 371--382. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Gupta, A., Kim, Y., and Urgaonkar, B. 2009. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'09). 229--240. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Halderman, J. A., Schoen, S. D., Heninger, N., Clarkson, W., Paul, W., Calandrino, J. A., Feldman, A. J., Appelbaum, J., and Felten, E. W. 2008. Lest we remember: Cold boot attacks on encryption keys. In Proceedings of the 17th Conference on Security Symposium. 45--60. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Huai, Y. 2008. Spin-transfer torque MRAM (STT-MRAM) challenges and prospects. AAPPS Bulle. 18, 6, 33--40.Google ScholarGoogle Scholar
  17. Ielmini, D., Lavizzari, S., Sharma, D., and Lacaita, A. 2007. Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation. In Proceedings of the IEEE International Electron Devices Meeting (IEDM'07).Google ScholarGoogle Scholar
  18. Ipek, E., Condit, J., Nightingale, E. B., Burger, D., and Moscibroda, T. 2010. Dynamically replicated memory: Building reliable systems from nanoscale resistive memories. In Proceedings of the 15th Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. ITRS 2007. International Technology Roadmap for Semiconductors. Process integration, devices & structures. http://www.itrs.net.Google ScholarGoogle Scholar
  20. Javanifard, J., Tanadi, T., Giduturi, H., Loe, K., Melcher, R., Khabiri, S., Hendrickson, N., Proescholdt, A., Ward, D., and Taylor, M. 2008. A 45nm self-aligned-contact process 1Gb NOR flash with 5MB/s program speed. In Proceedings of the IEEE International Solid-State Circuits Conference. (ISSCC'08. 424 --624.Google ScholarGoogle Scholar
  21. Kim, J. K., Lee, H. G., Choi, S., and Bahng, K. I. 2008. A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems. In Proceedings of the 8th ACM international Conference on Embedded Software (EMSOFT'08). 31--40. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Kong, J. and Zhou, H. 2010. Improving privacy and lifetime of PCM-based main memory. In Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10). 333--342.Google ScholarGoogle Scholar
  23. Lai, S. 2003. Current status of the phase change memory and its future. In Proceedings of the IEEE International Electron Devices Meeting (IEDM'03). 10.1.1--10.1.4.Google ScholarGoogle ScholarCross RefCross Ref
  24. Lam, C. 2007. Phase-change memory. In Proceedings of the 65th Annual Device Research Conference. 223--226.Google ScholarGoogle ScholarCross RefCross Ref
  25. Lee, B. C., Ipek, E., Mutlu, O., and Burger, D. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA'09). 2--13. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Lee, S.-W. and Moon, B. 2007. Design of flash-based DBMS: An in-page logging approach. In Proceedings of the ACM SIGMOD International Conference on Management of Data (SIGMOD'07). 55--66. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Lefurgy, C., Rajamani, K., Rawson, F., Felter, W., Kistler, M., and Keller, T. W. 2003. Energy management for commercial servers. Computer 36, 39--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Li, J. and Lam, C. 2011. Phase change memory. Sci. China Inform. Sci. 54, 1061--1072.Google ScholarGoogle ScholarCross RefCross Ref
  29. Lin, J.-T., Liao, Y.-B., Chiang, M.-H., Chiu, I.-H., Lin, C.-L., Hsu, W.-C., Chiang, P.-C., Sheu, S.-S., Hsu, Y.-Y., Liu, W.-H., Su, K.-L., Kao, M.-J., and Tsai, M.-J. 2009. Design optimization in write speed of multi-level cell application for phase change memory. In Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC'09). 525--528.Google ScholarGoogle Scholar
  30. MicronFlash. 2008. Micron collaborates with Sun Microsystems to extend lifespan of flash-based storage, achieves one million write cycles. http://news.micron.com/releases.cfm.Google ScholarGoogle Scholar
  31. MicronNumonyx. 2010. Numonyx introduces new phase change memory devices. http://investors.micron.com/releasedetail.cfm?ReleaseID=466859.Google ScholarGoogle Scholar
  32. Nirschl, T., Phipp, J., Happ, T., Burr, G., Rajendran, B., Lee, M.-H., Schrott, A., Yang, M., Breitwisch, M., Chen, C.-F., Joseph, E., Lamorey, M., Cheek, R., Chen, S.-H., Zaidi, S., Raoux, S., Chen, Y., Zhu, Y., Bergmann, R., Lung, H.-L., and Lam, C. 2007. Write strategies for 2 and 4-bit multi-level phase-change memory. In Proceedings of the IEEE International Electron Devices Meeting (IEDM'07). 461--464.Google ScholarGoogle Scholar
  33. Nobunaga, D., Abedifard, E., Roohparvar, F., Lee, J., Yu, E., Vahidimowlavi, A., Abraham, M., Talreja, S., Sundaram, R., Rozman, R., Vu, L., Chen, C. L., Chandrasekhar, U., Bains, R., Viajedor, V., Mak, W., Choi, M., Udeshi, D., Luo, M., Qureshi, S., Tsai, J., Jaffin, F., Liu, Y., and Mancinelli, M. 2008. A 50nm 8Gb NAND flash memory with 100MB/s program throughput and 200MB/s DDR interface. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'08). 426--625.Google ScholarGoogle Scholar
  34. Numonyx. 2008. The basics of phase change memory (PCM) technology. Technical White Paper. http://www.numonyx.com/Documents/WhitePapers/PCM_Basics_WP.pdf.Google ScholarGoogle Scholar
  35. NumonyxOmneo. 2010. Numonyx Omneo P8P PCM - 128-mbit parallel phase change memory (NP8P128A13BSM60E datasheet). http://www.alldatasheet.com/datasheet-pdf/pdf/354464/NUMONYX/NP8P128A13BSM60E.html.Google ScholarGoogle Scholar
  36. Ohta, T. 2011. Phase change memory and breakthrough technologies. IEEE Trans. Magnetics 47, 3, 613--619.Google ScholarGoogle ScholarCross RefCross Ref
  37. Ovshinsky, S. R. 1968. Reversible electrical switching phenomena in disordered structures. Physical Rev. Lett. 21, 20, 1450--1453.Google ScholarGoogle ScholarCross RefCross Ref
  38. Park, C., Talawar, P., Won, D., Jung, M., Im, J., Kim, S., and Choi, Y. 2006. A high performance controller for NAND flash-based solid state disk (NSSD). In Proceedings of the Non-Volatile Semiconductor Memory Workshop (IEEE NVSMW'06. 17--20.Google ScholarGoogle Scholar
  39. Park, Y., Lim, S.-H., Lee, C., and Park, K. H. 2008. PFFS: A scalable flash memory file system for the hybrid architecture of phase-change RAM and NAND flash. In Proceedings of the ACM Symposium on Applied Computing (SAC'08). 1498--1503. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Pirovano, A., Lacaita, A., Pellizzer, F., Kostylev, S., Benvenuti, A., and Bez, R. 2004a. Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials. IEEE Trans. Electron Devices 51, 5, 714--719.Google ScholarGoogle ScholarCross RefCross Ref
  41. Pirovano, A., Redaelli, A., Pellizzer, F., Ottogalli, F., Tosi, M., Ielmini, D., Lacaita, A., and Bez, R. 2004b. Reliability study of phase-change nonvolatile memories. IEEE Trans. Device Materials Reliab. 4, 3, 422--427.Google ScholarGoogle ScholarCross RefCross Ref
  42. Qureshi, M., Franceschini, M., and Lastras-Montano, L. 2010a. Improving read performance of phase change memories via write cancellation and write pausing. In Proceedings of the IEEE 16th International Symposium on High Performance Computer Architecture (HPCA'10). 1--11.Google ScholarGoogle Scholar
  43. Qureshi, M. K., Franceschini, M. M., Lastras-Montaño, L. A., and Karidis, J. P. 2010b. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10). 153--162. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Qureshi, M. K., Karidis, J., Franceschini, M., Srinivasan, V., Lastras, L., and Abali, B. 2009a. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'09). 14--23. Google ScholarGoogle ScholarDigital LibraryDigital Library
  45. Qureshi, M. K., Srinivasan, V., and Rivers, J. A. 2009b. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA'09). 24--33. Google ScholarGoogle ScholarDigital LibraryDigital Library
  46. Ramos, L. E., Gorbatov, E., and Bianchini, R. 2011. Page placement in hybrid memory systems. In Proceedings of the International Conference on Supercomputing (ICS'11). 85--95. Google ScholarGoogle ScholarDigital LibraryDigital Library
  47. Samsung. 2009. Samsung develops world's highest density DRAM chip (low-power 4Gb DDR3). http://www.samsung.com/global/business/semiconductor/newsView.do?news_id=975.Google ScholarGoogle Scholar
  48. Samsung. 2010. Samsung ships industry's first multi-chip package with a PRAM chip for handsets. http://www.samsung.com/us/news/newsRead.do?news_seq=18828.Google ScholarGoogle Scholar
  49. Samsung 2011. Samsung producing industry's highest density mobile DRAM, using 30nm-class technology. http://www.samsung.com/global/business/semiconductor/newsView.do?news_id=1238.Google ScholarGoogle Scholar
  50. Schechter, S., Loh, G. H., Straus, K., and Burger, D. 2010. Use ECP, not ECC, for hard failures in resistive memories. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  51. Seong, N. H., Woo, D. H., and Lee, H.-H. S. 2010a. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10). 383--394. Google ScholarGoogle ScholarDigital LibraryDigital Library
  52. Seong, N. H., Woo, D. H., Srinivasan, V., Rivers, J. A., and Lee, H.-H. S. 2010b. Safer: Stuck-at-fault error recovery for memories. In Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'43). IEEE Computer Society, Washington, DC, 115--124. Google ScholarGoogle ScholarDigital LibraryDigital Library
  53. Seznec, A. 2010. A phase change memory as a secure main memory. IEEE Comput. Architect. Lett. 9, 5--8. Google ScholarGoogle ScholarDigital LibraryDigital Library
  54. Sun, G., Joo, Y., Chen, Y., Niu, D., Xie, Y., Chen, Y., and Li, H. 2010. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In Proceedings of the IEEE 16th International Symposium on High Performance Computer Architecture (HPCA'10). 1--12.Google ScholarGoogle Scholar
  55. Thoziyoor, S., Ahn, J. H., Monchiero, M., Brockman, J. B., and Jouppi, N. P. 2008. A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. In Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA'08). 51--62. Google ScholarGoogle ScholarDigital LibraryDigital Library
  56. Toshiba. 2009. Toshiba announces world's first 512GB SSD laptop. http://news.cnet.com/8301-17938_105-10241140-1.html.Google ScholarGoogle Scholar
  57. Volos, H., Tack, A. J., and Swift, M. M. 2011. Mnemosyne: Lightweight persistent memory. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'11). 91--104. Google ScholarGoogle ScholarDigital LibraryDigital Library
  58. Wong, H., Raoux, S., Kim, S., Liang, J., Reifenberg, J., Rajendran, B., Asheghi, M., and Goodson, K. 2010. Phase change memory. Proc. IEEE.Google ScholarGoogle Scholar
  59. Yang, B.-D., Lee, J.-E., Kim, J.-S., Cho, J., Lee, S.-Y., and Yu, B.-G. 2007. A low power phase-change random access memory using a data-comparison write scheme. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'07). 3014--3017.Google ScholarGoogle Scholar
  60. Yoon, D. H., Muralimanohar, N., Chang, J., Ranganathan, P., Jouppi, N., and Erez, M. 2011. FREE-p: Protecting non-volatile memory against both hard and soft errors. In Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA'11). 466--477. Google ScholarGoogle ScholarDigital LibraryDigital Library
  61. Yoon, J. H., Nam, E. H., Seong, Y. J., Kim, H., Kim, B., Min, S. L., and Cho, Y. 2008. Chameleon: A high performance flash/FRAM hybrid solid state disk architecture. IEEE Comput. Architec. Lett. 7, 17--20. Google ScholarGoogle ScholarDigital LibraryDigital Library
  62. Zhang, W. and Li, T. 2009. Exploring phase change memory and 3d die-stacking for power/thermal friendly, fast and durable memory architectures. In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques. 101--112. Google ScholarGoogle ScholarDigital LibraryDigital Library
  63. Zhou, P., Zhao, B., Yang, J., and Zhang, Y. 2009. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA'09). 14--23. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Phase-change memory: An architectural perspective

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Computing Surveys
      ACM Computing Surveys  Volume 45, Issue 3
      June 2013
      575 pages
      ISSN:0360-0300
      EISSN:1557-7341
      DOI:10.1145/2480741
      Issue’s Table of Contents

      Copyright © 2013 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 3 July 2013
      • Accepted: 1 January 2012
      • Revised: 1 November 2011
      • Received: 1 August 2011
      Published in csur Volume 45, Issue 3

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader