Abstract
A three-dimensional (3D) integrated circuit (IC) with multiple dies vertically connected by through-silicon-via (TSV) offers many benefits over current 2D ICs. Multicore logic-memory die stacking has been considered as one candidate for 3D ICs by utilizing the TSV to provide high data bandwidth between logic and memory. However, 3D ICs suffer from the low-yield issue. This article proposes effective yield-enhancement techniques for multicore die-stacked 3D ICs. Two reconfiguration schemes are proposed to logically swap the positions of cores in the dies of 3D ICs such that the yield of 3D ICs is increased. Two algorithms also are proposed to determine the reconfiguration effectively. Simulation results show that the proposed reconfiguration schemes can achieve a yield gain ranging from 1% to 11%.
- A. Agarwal and M. Levy. 2007. The KILL rule for multicore. In Proceedings of the IEEE/ACM Design Automation Conference. 750--753. Google ScholarDigital Library
- S. Borkar. 2007. Thousand core chips: A technology perspective. In Proceedings of the IEEE/ACM Design Automation Conference. 746--749. Google ScholarDigital Library
- Ritwik Chatterjee, M. Fayolle, P. Leduc, et al. 2007. Three dimensional chip stacking using a wafer-to-wafer integration. In Proceedings of the IEEE International Interconnect Technology Conference. 81--83.Google ScholarCross Ref
- Y. Chen, D. Niu, Y. Xie, and K. Chakrabarty. 2010. Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 471--476. Google ScholarDigital Library
- C.-W. Chou, Y.-J. Huang, and J.-F. Li. 2010. Yield-enhancement techniques for 3D random access memories. In Proceedings of the IEEE International Symposium on VLSI Design, Automation, and Test. 104--107.Google Scholar
- C.-W. Chou, Y.-J. Huang, and J.-F. Li. 2013. A built-in self-repair scheme for 3D RAMs with interdie redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32, 4, 572--583. Google ScholarDigital Library
- D. K. de Vries. 2005. Investigation of gross die per wafer formulas. IEEE Trans. Semicond. Manuf. 18, 1, 136--139.Google ScholarCross Ref
- C. Ferri, S. Reda, and R. I. Bahar. 2008. Parametric yield management for 3D ICs: models and strategies for improvement. ACM J. Emerg. Technol. Comput. Syst. 4, 4, Article 19. Google ScholarDigital Library
- D. Geer. 2005. Chip makers turn to multicore processors. IEEE Micro 38, 5, 11--13. Google ScholarDigital Library
- Michael B. Healy, K. Athikulwongse, R. Goel, et al. 2010. Design and analysis of 3D-MAPS: a many-core 3D processor with stacked memory. In Proceedings of the IEEE Custom Integrated Circuits Conference. 1--4.Google ScholarCross Ref
- Ang-Chih Hsieh and Ting-Ting Hwang. 2012. TSV redundancy: architecture and design issues in 3-D IC. IEEE Trans. VLSI Syst. 20, 4, 711--722. Google ScholarDigital Library
- Y.-J. Hu, J.-F. Li, and Y.-J. Huang. 2009. 3-D content addressable memory architectures. In Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing. 59--64. Google ScholarDigital Library
- Y.-J. Huang and J.-F. Li. 2012. Built-in self-repair scheme for the TSVs in 3D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31, 10, 1600--1613. Google ScholarDigital Library
- P. Jacob, A. Zia, O. Erdogan, P. M. Belemjian, J.-W. Kim, M. Chu, R. P. Kraft, J. F. McDonald, and K. Bernstein. 2009. Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks. Proc. IEEE 97, 1, 108--122.Google ScholarCross Ref
- Ajai Jain, Babu Mandava, Janusz Rajski, and Nicolas C. Rumin. 1991. A fault-tolerant array processor designed for testability and self-reconfiguration. IEEE J. Solid-State Circuits 26, 5, 778--788.Google ScholarCross Ref
- JEDEC. 2011. JEDEC wide I/O single data rate. http://www.jedec.org/.Google Scholar
- L. Jiang, R. Ye, and Q. Xu. 2010. Yield enhancement for 3D-stacked memory by redundancy sharing across dies. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 230--234. Google ScholarDigital Library
- B. W. Johnson. 1989. Design and Analysis of Fault Tolerant Digital Systems. Addison-Wesley, Reading, MA.Google Scholar
- J.-S. Kim, C. S. Oh, H. Lee, et al. 2012. A 1.2V 12.8 GB/s 2Gb mobile wide-I/O DRAM with 4x128 I/Os using TSV based stacking. IEEE J. Solid-State Circuits 47, 1, 107--116.Google ScholarCross Ref
- J. C. Koob, D. A. Leder, R. J. Sung, T. L. Brandon, D. G. Elliott, B. F. Cockburn, and L.McIlrath. 2005. Design of a 3-D fully depleted SOI computational RAM. IEEE Trans. VLSI Syst. 13, 3, 358--369. Google ScholarDigital Library
- M. Koyanagi, T. Fukushima, and T. Tanaka. 2009. High-density through silicon vias for 3-D LSIs. Proc. IEEE 97, 1, 49--59.Google ScholarCross Ref
- J. Lee, K. Park, and S. Kang. 2012. Yield enhancement techniques for 3D memories by redundancy sharing among all layers. ITRI J. 34, 3, 388--398.Google Scholar
- J.-F. Li and C.-W. Wu. 2010. Is 3D integration an opportunity or just a hype?. In Proceedings of the IEEE Asia South Pacific Design and Automation Conference. 541--543. Google ScholarDigital Library
- Gabriel H. Loh. 2008. 3D-stacked memory architectures for multi-core processors. In Proceedings of the International Symposium on Computer Architecture. 453--464. Google ScholarDigital Library
- J.-Q. Lu. 2009. 3-D hyperintegration and packaging technologies for micro-nano systems. Proc. IEEE 97, 1, 18--30.Google ScholarCross Ref
- S. Makar, T. Altinis, N. Parkar, and J. Wu. 2007. Testing of Vega2, a chip multi-processor with spare processors. In Proceedings of the International Test Conference. 1--10.Google Scholar
- R. S. Patti. 2006. Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE 94, 6, 1214--1224.Google ScholarCross Ref
- V. F. Pavlidis and E. G. Friedman. 2009. Interconnect-based design methodologies for three-dimensional integrated circuits. Proc. IEEE 97, 1, 123--140.Google ScholarCross Ref
- S. Reda, G. Smith, and L. Smith. 2009. Maximizing the functional yield of wafer-to-wafer 3-D integration. IEEE Trans. VLSI Syst. 17, 9, 1357--1362. Google ScholarDigital Library
- Hideaki Saito, M. Nakajima, T. Okamoto, et al. 2009. A chip-stacked memory for on-chip SRAM-rich SoCs and processor. In Proceedings of the IEEE International Solid-State Circuits Conference. 60--61.Google ScholarCross Ref
- A. Sehgal, E. J. Marinissen, C.Wouters, H. Vranken, and K. Chakrabarty. 2005. Redundancy modelling and array yield analysis for repairable embedded memories. IEE Proc. Comput. Digital Tech. 152, 1, 97--106.Google ScholarCross Ref
- Semiconductor Industry Association. 2009. International Technology Roadmap for Semiconductors (ITRS).Google Scholar
- S. Shamshiri, P. Lisherness, S.-J. Pan, and K.-T. Cheng. 2008. A cost analysis framework for multi-core systems with spares. In Proceedings of the International Test Conference. Paper 5.3, 1--8.Google Scholar
- M. Taouil, S. Hamdioui, J. Verbree, and E. J. Marinissen. 2010. On maximizing the compound yield for 3D wafter-to-wafer stacked ICs. In Proceedings of the International Test Conference. 1--10.Google Scholar
- Jouke Verbree, Erik JanMarinissen, Philippe Roussel, and Dimitrios Velenis. 2010. On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. In Proceedings of the IEEE European Test Symposium. 36--41.Google ScholarCross Ref
- T. W. Williams and N. C. Brown. 1981. Defect level as a function of fault coverage. IEEE Trans. Comput. 30, 12, 987--988. Google ScholarDigital Library
- Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang. 2009. Impacts of though-DRAM vias in 3D processor-DRAM integrated systems. In Proceedings of the IEEE International 3D System Integration Conference. 1--6.Google Scholar
- Y. Xie, G. H. Loh, B. Black, and K. Bersnstein. 2006. Design space exploration for 3D architectures. ACM J. Emerg. Technol. Comput. Syst. 2, 2, 65--103. Google ScholarDigital Library
- Q. Xu, L. Jiang, H. Li, and B. Eklow. 2012. Yield enhancement for 3D-stacked ICs: recent advances and challenges. In Proceedings of the Asia South Pacific Design and Automation Conference. 731--737.Google Scholar
- Lei Zhang, YinheHan, Qiang Xu, XiaoWei Li, and Huawei Li. 2009a. On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems. IEEE Trans. VLSI Syst. 17, 9, 1173--1186. Google ScholarDigital Library
- T. Zhang, R. Micheloni, G. Zhang, Z. R. Huang, and J. J.-Q. Lu. 2009b. 3-D data storage power delivery, and RF/optical transceiver. Case studies of 3-D integration from system design perspectives. Proc. IEEE 97, 1, 161--174.Google ScholarCross Ref
Index Terms
- Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
Recommendations
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary
GLSVLSI '19: Proceedings of the 2019 on Great Lakes Symposium on VLSIMonolithic 3D (M3D) ICs provide a way to achieve high performance and low power designs within the same technology node, thereby bypassing the need for transistor scaling. M3D ICs have multiple 2D tiers sequentially fabricated on top of each other and ...
Parametric yield management for 3D ICs: Models and strategies for improvement
Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ...
Comments