Ing-Chao Lin
Skip Abstract Section
Abstract
Leakage power is a major design constraint in deep submicron technology and below. Meanwhile, transistor degradation due to Negative Bias Temperature Instability (NBTI) has emerged as one of the main reliability concerns in nanoscale technology. Gate sizing is a widely used technique to reduce circuit leakage, and this approach has recently attracted much attention with regard to improving circuits to tolerate NBTI. However, these studies only consider timing and area constraints, and many other important issues, such as slew and max-load, are missing. In this article, we present an efficient gate sizing framework that can reduce leakage and improve circuit reliability under timing constraints. Our algorithms consider slack, slew and max-load constraints. The benchmarks are those from ISPD 2012, which feature industrial design properties, including discrete cell sizes, nonconvex cell timing models, slew dependencies and constraints, as well as large design sizes. The experimental results obtained from ISPD 2012 benchmark circuits demonstrate that our approach can meet all the constraints and tolerated NBTI degradation with a power savings of 6.54% as compared with the traditional method.
- Bild, D. R., Bok, G. E., and Dick, R. P. 2009. Minimization of NBTI performance degradation using internal node control. In Proceedings of the ACM/IEEE Design, Automation and Test in Europe. 148--153. Google Scholar
Digital Library
- Chen, C. P., Chu, C. C. N., and Wong, D. F. 1999. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. CAD 18, 7, 1014--1025. Google ScholarDigital Library
- Chen, Y.-P., Fang, J.-W., and Chang, Y.-W. 2007. ECO timing optimization using spare cells. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. 530--535. Google ScholarDigital Library
- Chinnery, D. G. and Keutzer, K. 2005. Linear programming for sizing, Vth and Vdd assignment. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 149--154. Google ScholarDigital Library
- Calimera, A., Macii, E., and Poncino, M. 2009. NBTI-aware sleep transistor design for reliable power-gating. In Proceedings of the ACM Great Lakes Symposium on VLSI. 333--338. Google ScholarDigital Library
- Chandrakasan, A., Bowhill, W., and Fox, F. 2001. Design of High-Performance Microprocessor Circuits, IEEE Press. Google ScholarDigital Library
- Fleetwood, D. M.., Zhang, E. X., Shen, X., Zhang, C. X., Schrimpf, R. D., and Pantelides, S. T. 2013. Bias-temperature instabilities in silicon carbide MOS devices. In Bias Temperature Instability for Devices and Circuits, Tibor Grasse Ed., Springer, 661--675.Google Scholar
- Franco, J. and Kaczer, B. 2013. NBTI in (Si)Ge channel devices, In Bias Temperature Instability for Devices and Circuits, Tibor Grasse Ed., Springer, 615--641.Google Scholar
- Franco, J., Kaczer, B., Cho, M., Eneman, G., Groeseneken G., and Grasser, T., 2010. Improvements of NBTI reliability in SiGe p-FETs. In Proceedings of International Reliability Physics Symposium, 1082--10845.Google Scholar
- Huang, R., Wang, R., and Li, M. 2013. Characteristics of NBTI in Multi-gate FETs for Highly Scaled CMOS Technology. In Bias Temperature Instability for Devices and Circuits, Tibor Grasser Ed., Springer, 643--659.Google Scholar
- Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2006. Efficient transistor-level sizing technique under temporal performance degradation due to NBTI. In Proceedings of the IEEE International Conference on Computer Design. 216--221.Google Scholar
- Kang, K., Gangwal, S., Park, S., and Roy, K. 2008. NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution? In Proceedings of the ACM/IEEE Asian South Pacific Design Automation Conference. 726--731. Google ScholarDigital Library
- Kim T. H., Yu C. G., and Park, J. T. 2011. Concurrent NBTI and Hot-Carrier Degradation in p-Channel MuGFETs. IEEE Electron Device Lett. 32, 3, 294--296.Google ScholarCross Ref
- Kumar, S., Kim, C., and Sapatnekar, S. 2007. NBTI-aware synthesis of digital circuits. In Proceedings of the ACM/IEEE Design Automation Conference. 370--375. Google ScholarDigital Library
- Lillis, J., Cheng, C., and Lin, T. 1996. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid-State Circuits 31, 3, 437--447.Google ScholarCross Ref
- Liu, Y. and Hu, J. 2010. A new algorithm for simultaneous gate sizing and threshold voltage assignment. IEEE Trans. CAD 29, 2, 223--234. Google ScholarDigital Library
- Luo, T., Newmark, D., and Pan, D. Z. 2008. Total power optimization combining placement, sizing and multi-Vt through slack distribution management. In Proceedings of the ACM/IEEE Asian South Pacific Design Automation Conference. 352--357. Google ScholarDigital Library
- Lin, C.-H., Lin, I.-C., and Li, K.-H. 2011. TG-based technique for NBTI degradation and leakage optimization. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 133--138. Google ScholarDigital Library
- Lin, C.-H., Lin, I.-C., and Li, K.-H. 2013. Leakage and aging optimization using transmission gate-based technique. IEEE Trans. CAD 32, 1, 87--99. Google ScholarDigital Library
- Liu, C., Yu, T., Wang, R., Zhang, L., Huang, R., Kim, D.-W., Park, D., and Wang, Y. 2010. Negative-bias temperature instability in gate-all-around silicon nanowire MOSFETs: Characteristic modeling and the impact on circuit aging. IEEE Trans. Electron Devices, 57, 12, 3442--3450.Google ScholarCross Ref
- Ozdal, M. M., Amin, C., Ayupov, A., Burns, S., Wilke, G., and Zhuo, C. 2012. The ISPD-2012 discrete cell sizing contest and benchmark suite. In Proceedings of the International Symposium on Physical Design. 161--164. http://www.ispd.cc/contests/12/ispd2012_contest.html. Google ScholarDigital Library
- Ozdal, M. M., Burns, S., and Hu, J. 2011. Gate sizing and device technology selection algorithms for high performance industrial designs. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. 724--731. Google ScholarDigital Library
- Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2007. Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits. IEEE Trans. CAD. 26, 4, 743--751. Google ScholarDigital Library
- Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2006. Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits. In Proceedings of the ACM/IEEE Design, Automation and Test in Europe. 780--785. Google ScholarDigital Library
- Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., and Roy, K. 2005. Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron Device Lett. 26, 8, 560--562.Google ScholarCross Ref
- Reddy, V., Krishnan, A. T., Marshall, A., Rodriguez, J., Natarajan, S., Rost, T., and Krishnan, S. 2012. Impact of negative bias temperature instability on digital circuit reliability. In Proceedings of the IEEE International Reliability Physics Symposium. 248--253.Google Scholar
- Schroder, D. K. 2009. Bias temperature instability in silicon carbide. In Proceedings of International Semiconductor Device Research Symposium. 1--2.Google ScholarCross Ref
- Vattikonda, R., Wang W., and Cao Y. 2006. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In Proceedings of the ACM/IEEE Design Automation Conference. 1047--1052. Google ScholarDigital Library
- Wang, Y., Chen, X., Wang, W., and Cao, Y., Xie, Y., and Yang, H. 2011. Leakage power and circuit aging cooptimization by gate replacement techniques. IEEE Trans. VLSI 19, 4, 615--628. Google ScholarDigital Library
- Wang, J., Das, D., and Zhou, H. 2009. Gate sizing by lagrangian relaxation revisited. IEEE Trans. CAD 28, 7, 1071--1084. Google ScholarDigital Library
- Wang, W., Wei, Z., Yang, S., and Cao, Y. 2007. An efficient method to identify critical gates under circuit aging. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. 735--740. Google ScholarDigital Library
- Wang W., Yang, S., Bhardwaj, S., Vattikonda, R., Vrudhula, S., Liu, F., and Cao, Y. 2007. The impact of NBTI on the performance of combinational and sequential circuits. In Proceedings of the ACM/IEEE Design Automation Conference. 364--369. Google ScholarDigital Library
- Yang, X. and Saluja, K. 2007. Combating NBTI degradation via gate sizing. In Proceedings of the IEEE International Symposium on Quality Electronic Design. 47--52. Google ScholarDigital Library
Index Terms
- NBTI tolerance and leakage reduction using gate sizing
Recommendations
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown
VLSID '14: Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded SystemsNegative Bias Temperature Instability (NBTI) and Oxide Breakdown (OBD) are two key reliability concerns for nanometer VLSI circuits. Gate over-sizing has been done in the past to mitigate the effect of NBTI and aging to meet performance constraints. ...
Gate sizing: finFETs vs 32nm bulk MOSFETs
DAC '06: Proceedings of the 43rd annual Design Automation ConferenceFinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper gate sizing of finFET devices, and we ...
Gate leakage reduction for scaled devices using transistor stacking
In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Leff) of 25 nm ( oxide thickness = 1.1 nm), 50 nm ( oxide thickness = 1.5 nm) and 90 nm( oxide thickness = 2.5 nm) is studied using device ...
Comments