- ERB+ 95.Edmondson, J. E et al, "Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor", Digital Technical Journal, Vol. 7, No. 1,1995, pp. 119-135. Google ScholarDigital Library
- Intel 96.Intel Corporation, Pentium-Pro data book, 1996.Google Scholar
- JBD+ 93.3"ouppi, N., et al., "A 300-MHz 115-W 32-b Bipolar ECL Microprocessor", in IEEE Journal of Solid-State Circuits, Nov. 1993, pp. 1152-1165.Google Scholar
- KaGh 97.Kamble, M. B. and Ghose, tC, "Energy-Efficiency of VLSI Caches: A Comparative Study", in Prec. IEEE 10-th, Int'l, Conf. on VIii Design, Jan. 1997, pp. 261-267, Google ScholarDigital Library
- Larus 96.Larus, J., "SHM: A MIPS 2000 Simulator", available form Univ. W'm., CS ftp si~.Google Scholar
- Mon 96.Montanaro, J. et al., "A 160 MHz, 32b 0.5 W CMOS RISC Microprocessor", in IEEE ISSCC 1996 Digest of Papors, 1996.Google Scholar
- Ro 96.Rogers, A., "CL-.SPIM: A Cycle Level Simulator for the MIPS 2000", available form Univ. Wis., CS ftp site,Google Scholar
- Smith 82.Smith, A. J'., "Cache Memories", ACM Computing Surveys, Sept. 1982, pp. 473-530. Google ScholarDigital Library
- StBu 95.Stan, M.R. andBurleson,W. P.,"Bus-Invert Coding for Low-Power I/O", IEEE Trans. on VI.,SI Systems, March 1995, pp.49-58. Google ScholarDigital Library
- SuDe 95.Su, C. and Despain, A., "Cache Design Tradcoffs for Power and Performance Optimization: A Case Study", in Prec. of the Int'l. Sym. on Low Power Design, 1995, pp, 63-68, Google ScholarDigital Library
- WeEs 93.Weste, N. H. E. and Eshraghian K, Principles of CMOS VLSI Design, 2nd edition, Addison-Wesley, 1993. Google ScholarDigital Library
- Wijo 94.Wilton, S. E., and 3"ouppi, N.,"An Enhanced Access and Cycle Time Model for On-Chip Caches", DEC WRL Research Report 93/5, July 1994Google Scholar
- Analytical energy dissipation models for low-power caches
Recommendations
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches
MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecturePower dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus ...
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and designIn our quest to bring down the power consumption in low-power chip-multiprocessors, we have found that TLB and snoop accesses account for about 40% of the energy wasted by all L1 data-cache accesses. We have investigated the prospects of using virtual ...
Comments