Abstract
Memory consistency models, or memory models, allow both programmers and program language implementers to reason about concurrent accesses to one or more memory locations. Memory model specifications balance the often conflicting needs for precise semantics, implementation flexibility, and ease of understanding. Toward that end, popular programming languages like Java, C, and C++ have adopted memory models built on the conceptual foundation of Sequential Consistency for Data-Race-Free programs (SC for DRF). These SC for DRF languages were created with general-purpose homogeneous CPU systems in mind, and all assume a single, global memory address space. Such a uniform address space is usually power and performance prohibitive in heterogeneous Systems on Chips (SoCs), and for that reason most heterogeneous languages have adopted split address spaces and operations with nonglobal visibility.
There have recently been two attempts to bridge the disconnect between the CPU-centric assumptions of the SC for DRF framework and the realities of heterogeneous SoC architectures. Hower et al. proposed a class of Heterogeneous-Race-Free (HRF) memory models that provide a foundation for understanding many of the issues in heterogeneous memory models. At the same time, the Khronos Group developed the OpenCL 2.0 memory model that builds on the C++ memory model. The OpenCL 2.0 model includes features not addressed by HRF: primarily support for relaxed atomics and a property referred to as scope inclusion. In this article, we generalize HRF to allow formalization of and reasoning about more complicated models using OpenCL 2.0 as a point of reference. With that generalization, we (1) make the OpenCL 2.0 memory model more accessible by introducing a platform for feature comparisons to other models, (2) consider a number of shortcomings in the current OpenCL 2.0 model, and (3) propose changes that could be adopted by future OpenCL 2.0 revisions or by other, related, models.
- Sarita Adve. 2010. Data races are evil with no exceptions: Technical perspective. Commun. ACM 53, 11 (Nov. 2010), 84--84. Google ScholarDigital Library
- Sarita V. Adve and Mark D. Hill. 1990. Weak ordering—a new definition. In Proceedings of the International Symposium on Computer Architecture. ACM, New York, NY, 2--14. Google ScholarDigital Library
- Hans-J. Boehm. 2013. N3710: Specifying the absence of out of thin air results (LWG2265).Google Scholar
- Hans-J. Boehm and S. V Adve. 2008. Foundations of the C++ concurrency memory model. In Proceedings of the International Symposium on Programming Language Design and Implementation. Google ScholarDigital Library
- Hans-J. Boehm and Brian Demsky. 2014. Outlawing ghosts: Avoiding out-of-thin-air results. In Proceedings of the Workshop on Memory Systems Performance and Correctness (MSPC’14). ACM, New York, NY, Article 7, 6 pages. Google ScholarDigital Library
- Benedict R. Gaster, Derek Hower, and Lee Howes. 2015. HRF-Relaxed: Adapting HRF to the complexities of industrial heterogeneous memory models (Supplemental material). (Jan. 2015). Retrieved from http://benedictgaster.org/?page_id=278.Google ScholarDigital Library
- Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop Gupta, and John Hennessy. 1990. Memory consistency and event ordering in scalable shared-memory multiprocessors. In Proceedings of the 17th Annual International Symposium on Computer Architecture (ISCA’90). ACM, New York, NY, 15--26. DOI:http://dx.doi.org/10.1145/325164.325102 Google ScholarDigital Library
- Blake A. Hechtman, Shuai Che, Derek R. Hower, Yingying Tian, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. 2014. QuickRelease: A throughput-oriented approach to release consistency on GPUs. In HPCA. 189--200.Google Scholar
- Derek R. Hower, Blake A. Hechtman, Bradford M. Beckmann, Benedict R. Gaster, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. 2014. Heterogeneous-race-free memory models. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (APLOS’14). ACM, New York, NY, 427--40. Google ScholarDigital Library
- HSA Foundation. 2012. Heterogeneous System Architecture: A Technical Review.Google Scholar
- ISO. International Organization for Standardization. 2011. ISO/IEC 14882:2011 information technology—programming languages—C++.Google Scholar
- Leslie Lamport. 1979. A new approach to proving the correctness of multiprocess programs. ACM Trans. Program. Lang. Syst. 1, 1 (Jan. 1979), 84--97. Google ScholarDigital Library
- Brandon Lucia, Luis Ceze, Karin Strauss, Shaz Qadeer, and Hans-J. Boehm. 2010. Conflict exceptions: Simplifying concurrent language semantics with precise hardware exceptions for data-races. In Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA’10). ACM, New York, NY, 210--221. DOI:http://dx.doi.org/10.1145/1815961.1815987 Google ScholarDigital Library
- Daniel Marino, Abhayendra Singh, Todd Millstein, Madanlal Musuvathi, and Satish Narayanasamy. 2010. DRFX: A simple and efficient memory model for concurrent programming languages. In Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI’10). ACM, New York, NY, 351--362. DOI:http://dx.doi.org/10.1145/1806596.1806636 Google ScholarDigital Library
- NVIDIA Corporation. 2013. CUDA 5.5 C Programming Guide.Google Scholar
- Oracle. 2014. The Java Langauge Specification.Google Scholar
- Herb Sutter. 2012. Atomic weapons: The C++ memory model and modern hardware. In C++ and Beyond.Google Scholar
Index Terms
- HRF-Relaxed: Adapting HRF to the Complexities of Industrial Heterogeneous Memory Models
Recommendations
Relaxed memory models: an operational approach
POPL '09Memory models define an interface between programs written in some language and their implementation, determining which behaviour the memory (and thus a program) is allowed to have in a given model. A minimal guarantee memory models should provide to ...
Relaxed memory models: an operational approach
POPL '09: Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languagesMemory models define an interface between programs written in some language and their implementation, determining which behaviour the memory (and thus a program) is allowed to have in a given model. A minimal guarantee memory models should provide to ...
Toward a Better Defined SYCL Memory Consistency Model
IWOCL '21: Proceedings of the 9th International Workshop on OpenCLA memory consistency model is a key component of a parallel programming model that describes guaranteed behavior for applications and valid optimizations for implementers. The SYCL 2020 specification took a step forward by adopting the atomic_ref syntax ...
Comments