Ching-Hwa Cheng
Abstract
It has been proposed that small amounts of energy dissipate when transfer through a rising Vdd. In typical power gate circuits, the PMOS transistors (PSW) reduce the leakage of power by shutting off outer Vdd to the idle blocks. We expand this technique by utilizing active PSW, which are turned on and off by a clock signal. The proposed SCKVdd technique combines the power source gated mechanism and clock signal to generate stable progressive rising voltage to suppress peak and average currents effectively. The SCKVdd technique is a scalable, clock-controlled, self-stabilized voltage technique. This technique is easily implemented in generic digital circuits to reduce power dissipation. A normal CMOS circuit shows a dynamic power consumption increase proportional to the clock frequency. SCKVdd results in a lower-than-usual frequency dependency, and is suitable for high speed clock circuits. SCKVdd can be integrated with frequency, voltage scaling and an activated PSW number to implement an efficient power-performance trade-off mechanism. In experiments that investigated constant Vdd for MPEG VLD chips, power dissipation savings were in the range of 42% to 54% with only a small delay penalty.
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Index Terms
- SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits
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