Michael Gasteier
Abstract
In this article, we present an approach to automatic generation of communication topologies for statically scheduled systems of subsystems. Given a specification containing a set of processes that communicate via abstract send and receive functions, we show how a cost-efficient communication topology consisting of one or more buses without arbitration scheme can be set up for such applications.
- CHOU, P. H., ORTEGA, R. B., AND BORRIELLO, G. 1995. The Chinook hardware/software co-synthesis system. In Proceedings of the Eighth International Symposium on System Synthesis (Cannes, France, Sept. 13-15, 1995), P. G. Paulin and F. Mavaddat, Eds. ACM Press, New York, NY, 22-27. Google Scholar
- FILO, B., Ku, D. C., AND DE MICHELI, G. 1993. Interface optimization for concurrent systems under timing constraints. IEEE Trans. Very Large Scale Integr. Syst. 1, 3 (Sept.), 268-281.Google Scholar
- GASTEIER, M. AND GLESNER, M. 1996. Co-simulation of mixed HW/SW systems (Co-simulation gemischter HW/SW-Systeme). In Hardwarebeschreibungssprachen und Modellierungsparadigmen (GI/ITG/GME-Workshop) (Darmstadt, Germany, Feb. 1996). 60-69.Google Scholar
- GASTEIER, M., HOLLSTEIN, T., M NCH, M., AND GLESNER, M. 1996. An interactive approach to hardware/software co-design. In Proceedings of IFIP Workshop on Logic and Architecture Synthesis 96 (Grenoble, France, Dec. 1996). 211-218.Google Scholar
- GASTEIER, M., M NCH, M., AND GLESNER, M. 1998. Generation of interconnect topologies for communication synthesis. In Proceedings of the Conference on Design, Automation and Test in Europe 98. Google Scholar
- LIU, M. N. 1996. MPEG decoder architecture for embedded applications. In Proceedings of the ICCE 1996 (Chicago, IL).Google Scholar
- NARAYAN, S. AND GAJSKI, D. 1994. Synthesis of system level bus interfaces. In Proceedings of the European Design and Test Conference 94 (Paris, France, Feb. 1994). 395-399.Google Scholar
- VAN ROMPAEY, K., VERKEST, D., BOLSENS, I., AND DE MAN, H. 1996. CoWare -- A design environment for heterogeneous hardware/software systems. In Proceedings of the European Design Automation Conference 96 (Geneva, Switzerland, Sept. 1996). 252-257. Google Scholar
- YEN, T.-Y. AND WOLF, W. 1995. Communication synthesis for distrbuted embedded systems. In Proceedings of the 1995 IEEE/ACM International Conference on Computer- Aided Design (ICCAD-95, San Jose, CA, Nov. 5-9, 1995), R. Rudell, Ed. IEEE Computer Society Press, Los Alamitos, CA, 288-294. Google Scholar
Index Terms
- Bus-based communication synthesis on system level
Recommendations
Automated bus generation for multiprocessor SoC design
The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call ...
Floorplan-aware automated synthesis of bus-based communication architectures
DAC '05: Proceedings of the 42nd annual Design Automation ConferenceAs System-on-Chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to ...
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models
With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented ...
Comments