Stefan Pees
- 1.M. Hartoog, J. Rowson, et al., "Generation of software tools from processor descriptions for hardware/software codesign," in Proc. of the Design Automation Conference (DA C), Jun. 1997. Google Scholar
Digital Library
- 2.J. Rowson, "Hardware/Software co-simulation," in Proc. of the A CM/IEEE Design Automation Conference (DA C), 1994.Google Scholar
- 3.V. Zivojnovic, S. Tjiang, and H. Meyr, "Compiled simulation of programmable DSP architectures," in Proc. of IEEE Workshop on VLSI Signal Processing, (Sakai, Osaka), pp. 187-196, Oct. 1995.Google Scholar
- 4.S. Pees, V. Zivojnovic, A. Ropers, and H. Meyr, "Fast Simulation of the TI TMS 320C54x DSP," in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT), (San Diego), pp. 995-999, Sep. 1997.Google Scholar
- 5.M. Barbacci, "Instruction set processor specifications (ISPS): The notation and its application," IEEE Transactions on Computers, vol. C-30, pp. 24-40, Jan. 1981.Google Scholar
- 6.A. Fauth and A. Knoll, "Automatic generation of DSP program development tools using a machine description formalism," in Proc. of the ICASSP- Minneapolis, Minn., 1993.Google Scholar
- 7.V. Zivojnovic, S. Pees, and H. Meyr, "LISA- machine description language and generic machine model for HW/SW co-design," in Proceedings of the IEEE Workshop on VLSI Signal Processing, (San Francisco), Oct. 1996.Google Scholar
- 8.S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr, "LISA- Machine Description Language for Cycle- Accurate Models of Programmable DSP Architectures," in Proceedings of the Design Automation Conference (DA C), (N~w Orl~), J~ 1999. Google ScholarDigital Library
- 9.A. Fauth, M. Freericks, and A. Knoll, "Generation of hardware machine models from instruction set descriptions," in Proc. of the IEEE Workshop on VLSI Dighal Processing, 1993.Google Scholar
- 10.G. Hadjiyiannis, S. Hanono, and S. Devadas, "ISDL: An instruction set description language for retargetability," in Proc. of the Design Automation Conference (DA C), J~. 1997. Google ScholarDigital Library
- 11.A. Halambi, P. Grun, et al., "EXPRESSION: A language for architecture exploration through compiler/simulator retargetability," in Proc. of the Conference on Design, Automation ~ Test in Europe (DATE), Mar. 1999. Google ScholarDigital Library
- 12.C. Siska, 'CA processor description language supporting retargetable multi-pipeline DSP program development tools," in Proc. of the Int. Symposium on System Synthesis (ISSS), Dec. 1998. Google ScholarDigital Library
- 13.Z. Barzilai, et al., "HSS - A high speed simulator," IEEE Trans. on CAD, vol. CAD-6, pp. 601-616, July 1987. 1987.Google Scholar
Index Terms
- Retargeting of compiled simulators for digital signal processors using a machine description language
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