Samy Meftali
ABSTRACT
In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.
- 1.S.V Adve, V.S Pai, P. Ranganathan, "Recent Advances in Memory Consistency Models for Hardware Shared Memory Systems", Special issue on distributed Shared-Memory Systems, Mars 1999.Google Scholar
- 2.C. Amza, A. Cox, S. Dwarkadas, L. Jin & al, "Adaptive Protocols for Software Distributed Shared Memory", Special issue on distributed Shared-Memory Systems, Mars 1999.Google Scholar
- 3.A. Baghdadi, D. Lyonnard, N-E. Zergainoh, A.A. Jerraya, "An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC", Proc. of DATE 2001, Mar 2001. Google ScholarDigital Library
- 4.F. Cathoor & al, Custom Memory Management Methodology, Kluwer Academic Publishers, 1998. Google ScholarDigital Library
- 5.F. Cathoor, S. Wuytack & al, "System level transformations for low power data transfer and storage", in paper collection "low power CMOS design >>, IEEE Press, pp.609-618, 1998.Google Scholar
- 6.D. Culler, J.P. Singh, A. Gupta, "Parallel computer architecture :A Hardware/Software approach", Maurgan Kauffman publishers, August 1998. Google ScholarDigital Library
- 7.K. Danckaert, F. Cathoor & al, "System-level memory optimization for hardware-software co-design", Proc. of Workshop on hardware/software co-design, Braunschweig, Germany, pp.55-59, March 1997. Google ScholarDigital Library
- 8.L. Gauthier, S. Yoo, A.A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software", Proc. of DATE conference, Munich, March 2001. Google ScholarDigital Library
- 9.J. Hennessy, M. Heinrich, A. Gupta, "Cache-Coherent Distributed Shared Memory : Perspectives on Its Development and Future Challenges", Special issue on distributed Shared-Memory Systems, March 1999.Google Scholar
- 10.IBM, Inc. "28.4G Packet Rooting Switch", Networking Technology Data sheets, http://www.chips.ibm.com/techlib/products/commun/datashe ets.html.Google Scholar
- 11.H.F. Leung, H.F. Ting, "An Optimal Algorithm for Global Termination Detection in Shared-Memory Asynchronous Multiprocessor Systems", IEEE Transactions on parallel and distributed systems, May 1997. Google ScholarDigital Library
- 12.Y. Li, W. Wolf, "Allocation of Multirate Systems on Multiprocessors with Memory Hierarchy Modeling and Optimization", Proc. of CODES/CASHE '97, Braunschweig, Germany, March, 1997.Google Scholar
- 13.Y. Li, W. Wolf, "Hardware/Software Co-Synthesis with Memory Hierarchies", IEEE transaction on computer-aided design of integrated circuit and Systems, October 1999. Google ScholarDigital Library
- 14.D. Lyonnard, S. Yoo, A. Baghdadi, A.A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip', Proc. of DAC 2001, June 2001, Las Vegas, Nevada, USA. Google ScholarDigital Library
- 15.P. R. Panda, N. Dutt, A. Nicolau, Memory Issues in Embedded Systems-on-chip : Optimization and exploration, Kluwer Academic Publishers, 1999. Google ScholarDigital Library
- 16.J. Protic, M. Tomasevic, V. Milutinovic, "Distributed Shared Memory : Concepts and Systems", IEEE Parallel & Distributed Technology; Summer 1996. Google ScholarDigital Library
- 17.SystemC << user's manual >>, http://www.systemc.org.Google Scholar
- 18.S. Wuytack, J.P. Diguet & al, "Formalized methodology for data reuse exploration for low-power hierarchical memory mapping", IEEE Trans, on VLSI Systems, Vol6, 1998. Google ScholarDigital Library
Recommendations
Optimal memory controller placement for chip multiprocessor
CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisIn this paper, we analyze and compare different placements of memory controllers for Chip Multiprocessors (CMPs). As the number of cores increases, Network-on-Chip (NoC) based architectures are proposed as a promising interconnect technique for CMP. The ...
Application-Specific Network-on-Chip synthesis with flexible router Placement
Network-on-Chip (NoC) has been proposed as a possible solution to the communication problem in nanoscale System-on-Chip (SoC) design. NoC architectures with optimized application-specific topologies have been found to be superior to the regular ...
A real-time Java chip-multiprocessor
Chip-multiprocessors are an emerging trend for embedded systems. In this article, we introduce a real-time Java multiprocessor called JopCMP. It is a symmetric shared-memory multiprocessor, and consists of up to eight Java Optimized Processor (JOP) ...
Comments