Terry Tao Ye
ABSTRACT
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs.
- H. Jonathan Chao, Cheuk H. Lam, Eiji Oki "Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers" Wiley Interscience 2001 Google Scholar
Digital Library
- Wassal, A.G.; Hasan, M.A. "Low-power system-level design of VLSI packet switching fabrics" CAD of Integrated Circuits and Systems, IEEE Transactions on, June 2001 Google ScholarDigital Library
- C. Patel, S. Chai, S. Yalamanchili, D. Shimmel, "Power constrained design of multiprocessor interconnection networks," Int'l Conference on Computer Design, 1997. Google ScholarDigital Library
- Langen, D.; Brinkmann, A.; Ruckert, U. "High level estimation of the area and power consumption of on-chip interconnects," IEEE Int'l ASIC/SOC Conference, 2000.Google Scholar
- R. Ho, K. Mai, M. Horowitz, "The Future of wires," Proceedings of the IEEE, April 2001.Google Scholar
- C. D. Thompson, "A Complexity Theory for VLSI, PhD thesis", Carnegie-Mellon University, August 1980 Google ScholarDigital Library
- Andre DeHon, "Compact, Multilayer Layout for Butterfly Fat-free" 12th ACM Sym. on Parallel Algorithms and Architectures, 2000 Google ScholarDigital Library
- E. Geethanjali, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, "Memory System Energy: Influence of Hardware-Software Optimizations", Int'l Sym on Low Power Design and Electronics, July 2000.Google Scholar
- Wen-Tsong Shiue; Chakrabarti, C. "Memory exploration for low power, embedded systems", 36th Design Automation Conference, 1999. Proceedings. Google ScholarDigital Library
- Moustafa A. Youssef, M. N. El-Derini and H. H. Aly "Structure and Performance Evaluation of a Replicated Banyan Network Based ATM Switch" IEEE Sym. on Computers and Communications 1999 Google ScholarDigital Library
- Oktug, S.F.; Caglayan, M.U. "Design and performance evaluation of a banyan network based interconnection structure for ATM switches", Selected Areas in Communications, IEEE Journal on, June 1997 Google ScholarDigital Library
Index Terms
- Analysis of power consumption on switch fabrics in network routers
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