ABSTRACT
Although several recent papers have proposed architectural support for program debugging and profiling, most processors do not yet provide even basic facilities, such as an instruction counter. As a result, system developers have been forced to invent software solutions. This paper describes our implementation of a software instruction counter for program debugging. We show that an instruction counter can be reasonably implemented in software, often with less than 10% execution overhead. Our experience suggests that a hardware instruction counter is not necessary for a practical implementation of watch-points and reverse execution, however it will make program instrumentation much easier for the system developer.
- 1.T. Cargill and B. Locanthi. Cheap hardware support for software debugging and profiling. In Proc. of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pages 82-83, Palo Alto, CA, Oct. 1987. Google ScholarCross Ref
- 2.Digital Equipment Corporation. VAX Architecture Handbook. Digital Equipment Corporation, Maynard, MA, 1981.Google Scholar
- 3.I. J. P. Elshoff. A distributed debugger for Amoeba. In Proc. of the $IGPLAN/$IGOP$ Workshop on Parallel and Distributed Debugging, pages 1-10, Madison, WI, May 1988. Google ScholarDigital Library
- 4.R. Fowler, T. LeBlanc, and J. Mellor-Crummey. An integrated approach to parallel program debugging and performance analysis on largescale multiprocessors. In Proc. of the SIG- PLAN/$IGOP$ Workshop on Parallel and Distributed Debugging, pages 163-173, Madison, WI, May 1988. Google ScholarDigital Library
- 5.R. B. Gardner. SPARC scalable processor architecture. Sun Technology, 1(3):42-55, 1988.Google Scholar
- 6.S. Graham, P. Kessler, and M. McKusick. gprof: A call graph execution profiler. In Proc. of the SIGPLAN '82 Symposium on Compiler Construction, pages 120-126. SIGPLAN notices, Vol 17, No. 6, june 1982. Google ScholarDigital Library
- 7.Hewlett-Packard. Precision architecture and Instruction Reference Manual. Hewlett-Packard Company, Rockville, MD, 1987.Google Scholar
- 8.M. Johnson. Some requirements for architectural support of software debugging. In Proc. of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 140-148, Palo Alto, CA, Mar. 1982. Google ScholarDigital Library
- 9.T. J. LeBlanc and J. M. Mellor-Crummey. Debugging parallel programs with Instant Replay. {EEE Transactions on Computers, C-36(4):471- 482, Apr. 1987. Google ScholarDigital Library
- 10.R. McLear, D. Scheibelhut, and E. Tammaru. Guidelines for creating a debuggable processor. In Proc. of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 100-106, Palo Alto, CA, Mar. 1982. Google ScholarDigital Library
- 11.Motorola. 68020 3~-bit Microprocessor User's Manual, Second Edition. Prentice Hall, Englewood Cliffs, NJ, 1985. Google ScholarDigital Library
- 12.J. Moussouris, L. Crudele, D. Freitas, C. Hansen, E. Hudson, R. March, S. Przybylski, T. Riordan, C. Rowen, and D. Van't Hof. A CMOS RISC processor with integrated system functions. In Proc. of the 1986 COMPCON. IEEE, Mar. 1986.Google Scholar
- 13.S. S. Muchnick. Optimizing compilers for SPARC. Sun Technology, 1(3):64-77, 1988.Google Scholar
- 14.D. Z. Pan and M. A. Linton. Supporting reverse execution of parallel programs. In Proc. of ~he SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, pages 124-129, Madison, WI, May 1988. Google ScholarDigital Library
- 15.R. Richardson. Dhrystone 2.1 benchmark. Usenet Distribution, Dec. 1988.Google Scholar
- 16.D. W. Wall and M. L. Powell. The Mahler experience' Using an intermediate language as the machine description. In Proc. of the ~nd International Conference on Architectural Support for Programming Languages and Operating Systems, pages 100-104, Palo Alto, CA, Oct. 1987. Google ScholarCross Ref
- 17.R. P. Weicker. Dhrystone benchmark: Rationale for version 2 and measurement rules. $IGPLAN Notices, pages 49-62, Aug. 1988. Google ScholarDigital Library
Index Terms
- A software instruction counter
Recommendations
A software instruction counter
Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systemsAlthough several recent papers have proposed architectural support for program debugging and profiling, most processors do not yet provide even basic facilities, such as an instruction counter. As a result, system developers have been forced to invent ...
Automatic custom instruction identification for application-specific instruction set processors
The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...
Increasing the instruction fetch rate via block-structured instruction set architectures
MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on MicroarchitectureTo exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance ...
Comments