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A software instruction counter

Published:01 April 1989Publication History

ABSTRACT

Although several recent papers have proposed architectural support for program debugging and profiling, most processors do not yet provide even basic facilities, such as an instruction counter. As a result, system developers have been forced to invent software solutions. This paper describes our implementation of a software instruction counter for program debugging. We show that an instruction counter can be reasonably implemented in software, often with less than 10% execution overhead. Our experience suggests that a hardware instruction counter is not necessary for a practical implementation of watch-points and reverse execution, however it will make program instrumentation much easier for the system developer.

References

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            • Published in

              cover image ACM Conferences
              ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems
              April 1989
              303 pages
              ISBN:0897913000
              DOI:10.1145/70082
              • cover image ACM SIGARCH Computer Architecture News
                ACM SIGARCH Computer Architecture News  Volume 17, Issue 2
                Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems
                April 1989
                291 pages
                ISSN:0163-5964
                DOI:10.1145/68182
                Issue’s Table of Contents

              Copyright © 1989 ACM

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              Publication History

              • Published: 1 April 1989

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