V. G. Grafe
Abstract
The εpsilon dataflow architecture is designed for high speed uniprocessor execution as well as for parallel operation in a multiprocessor system. The εpsilon architecture directly matches ready operands, thus eliminating the need for associative matching stores. εpsilon also supports low cost data fan out and critical sections. A 10 MFLOPS CMOS/TTL processor prototype is running and its performance has been measured with several benchmarks. The prototype processor has demonstrated sustained performance exceeding that of comparable control flow processors running at higher clock rates (three times faster than a 20 Mhz transputer and 24 times faster than a Sun on a suite of arithmetic tests, for example).
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Index Terms
- The Epsilon dataflow processor
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