Karthik Natarajan
Stephen W. Keckler
Doug Burger
ABSTRACT
The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wide-issue, highly speculative cores. Microarchitectural speculation, such as branch prediction, increases instruction throughput but carries a power burden due to wasted power for mis-speculated instructions. Pipeline over-provisioning supplies excess resources which often go unused. In this paper, we use our detailed performance and power model for an Alpha 21264 to measure both the useful energy and the wasted effort due to mis-speculation and over-provisioning. Our experiments show that flushed instructions account for approximately 6% of total energy, while over-provisioning imposes a tax of 17% on average. These results suggest opportunities for power savings and energy efficiency throughout microprocessor pipelines.
- D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual Symposium on Computer Architecture (ISCA), pages 83--94, 2000.]] Google Scholar
Digital Library
- A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D. Albonesi. An adaptive issue queue for reduced power at high performance. In Workshop on Power-Aware Computers Systems, held in conjunction with ASPLOS, Nov 2000.]] Google ScholarDigital Library
- Compaq Computer Corporation. Alpha 21264 Microprocessor Hardware Reference Manual, July 1999.]]Google Scholar
- Compaq Computer Corporation. Compiler Writer's Guide for the Alpha 21264, 1999.]]Google Scholar
- R. Desikan, D. Burger, and S. W. Keckler. Measuring experimental error in microprocessor simulation. In Proceedings of the 28th Annual Symposium on Computer Architecture, pages 266--277, 2001.]] Google ScholarDigital Library
- D. Folegnani and A. Gonzalez. Energy-effective issue logic. In 28th International Symposium on Computer Architecture, pages 230--239, July 2001.]] Google ScholarDigital Library
- B. A. Gieseke, R. L. Allmon, D. W. Bailey, B. J. Benschneider, S. M. Britton, J. D. Clouser, H. R. F. III, J. A. Farrell, M. K. Gowan, C. L. Houghton, J. B. Keller, T. H. Lee, D. Leibholz, S. C. Lowell, M. D. Matson, R. J. Matthew, V. Peng, M. D. Quinn, D. A. Priore, M. J. Smith, and K. E. Wilcox. A 600 Mhz superscalar RISC microprocessor with out-of-order execution. In IEEE International Solid-State Circuits Conference, pages 176--177, 451, February 1997.]]Google Scholar
- M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the Alpha 21264 microprocessor. In Proceedings of the 35th Design Automation Conference, pages 726--731, 1998.]] Google ScholarDigital Library
- A. Iyer and D. Marculescu. Run--time scaling of microarchitecture resources in a processor for energy savings. In Cool Chips Workshop, held in conjunction with MICRO--33, 2000.]]Google Scholar
- T. Karkhanis, J. E. Smith, and P. Bose. Saving energy with just in time instruction delivery. In Proceedings of the 2002 International Symposium on Low Power Electronics and Design, pages 178 -- 183, 2002.]] Google ScholarDigital Library
- R. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24--36, March/April 1999.]] Google ScholarDigital Library
- S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the 25th Annual Symposium on Computer Architecture (ISCA), pages 132--141, 1998.]] Google ScholarDigital Library
- M. Matson, D. Bailey, S. Bell, L. Biro, S. Butler, J. Clouser, J. Farrell, M. Gowan, D. Priore, and K. Wilcox. Circuit implementation of a 600mhz superscalar RISC microprocessor. In Proceedings of the International Conference on Computer Design, pages 104--110, 1998.]] Google ScholarDigital Library
- D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. Power issues related to branch prediction. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pages 211 --222, 2002.]] Google ScholarDigital Library
- D. Ponomarev, G. Kucuk, and K. Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In 34th International Symposium on Microarchitecture, pages 90--101, Dec 2001.]] Google ScholarDigital Library
- K. Wilcox and S. Manne. Alpha processors: A history of power issues and a look to the future. In Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design, pages 16--37, 1999.]]Google Scholar
Index Terms
- Microprocessor pipeline energy analysis
Recommendations
An evaluation of speculative instruction execution on simultaneous multithreaded processors
Modern superscalar processors rely heavily on speculative execution for performance. For example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for SPECINT95 are speculative. Without speculation, processor resources ...
Dynamic MIPS Rate Stabilization for Complex Processors
Modern microprocessor cores reach their high performance levels with the help of high clock rates, parallel and speculative execution of a large number of instructions, and vast cache hierarchies. Modern cores also have adaptive features to regulate ...
Power consumption and reduction in a real, commercial multimedia core
CF '09: Proceedings of the 6th ACM conference on Computing frontiersPeak power and total energy consumption are key factors in the design of embedded microprocessors. Many techniques have been shown to provide great reductions in peak power and/or energy consumption. Unfortunately, several unrealistic assumptions are ...
Comments