Rajeev Krishna
ABSTRACT
The proliferation of computing technology to low power domains such as hand--held devices has lead to increased interest in portable interface technologies, with particular interest in speech recognition. The computational demands of robust, large vocabulary speech recognition systems, however, are currently prohibitive for such low power devices. This work begins anexploration of domain specific characteristics of speech recognition that might be exploited to achieve the requisite performance within the power constraints of such devices. We focus primarily on architectural techniques to exploit the massive amounts of potential thread level parallelism apparent in this application domain, and consider the performance / power trade-offs of such architectures. Our results show that a simple, multi-threaded, multi-pipelined processor architecture can significantly improve the performance of the time-consuming search phase of modern speech recognition algorithms, and may reduce overall energy consumption by drastically reducing dissipation of static power. We also show that the primary hurdle to achieving these performance benefits is the data request rate into the memory system, and consider some initial solutions to this problem.
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Index Terms
- Architectural optimizations for low-power, real-time speech recognition
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Reviews
Klaus K. Obermeier
Ever wondered how much continuous speech recognition could be done with one AA battery__?__ Eighteen thousand, 180,000, or even 1.8 million words__?__ Given an imputed demand for speech recognition on handheld devices, the dilemma is clear: massive parallel processing algorithms face severely limited AA battery power reservoirs. The authors argue that a simplified multi-threaded architecture that uses sublanguage information and decentralized controllers to reduce combinatorics in processing speech improves search efficiency, cuts down on the rate of data requests into the memory system, and, consequently, uses less power. The paper briefly introduces the state-of-the-art of speech processing, succinctly presents the authors’ proposal for a system architecture that could effectively be used for handheld devices, and presents a thorough, seven-page performance evaluation, before concluding with a cogent summary of related work and future research directions. The findings are threefold. First, high-concurrency execution environments with latency tolerance improve speech recognition. Second, reduction of static power dissipation leads to less energy consumption for a given task. Third, the crux in improving performance lies in optimizing the memory system, and reducing heat dissipation during power consumption. The authors extrapolate a performance of about 95 to 100 words per minute (18,000 words) for three hours of AA battery life. The do-ability is almost certain; the actual usability is a different story. Until speech recognizers go beyond is-this-what-you-mean confirmation prompts, and handle rudimentary dialogue without repetitive user input, battery life takes a back seat to the creature comforts of real-life spoken interaction. Online Computing Reviews Service
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