- Ande67.Anderson, D.W., Sparacio, F.J., and Tomasulo, R.M., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling". IBM Journal, Vol.9, No.25, January 1967, pp. 8-24.Google ScholarDigital Library
- Arga88.Agarwal, A., Simoni, R. Hennessy, J., and Horowitz, M., "An Evaluation of Directory Schemes for Cache Coherency". Proc. of the 15th Annual Int. Syrup. on Comp. Arch., Honolulu, Hawaii, June 1988, pp. 280- 289. Google ScholarDigital Library
- Arga89.Agarwal, A., Horowitz, M., and Hennessy, L, "An Analytical Cache Model". ACM Trans. on Comp. Sys., Vol.7, no.2, May 1989, pp. 184-215. Google ScholarDigital Library
- Arvi87.Arvind, and Ianucci, R.A., "Two Ftmdamental Issues in Multiprocessing". Proc. of DFVLR - Conf. 1987 on Parallel Proc. in Sc. and Eng., West Germany, June 1987, pp. 61-88. Google ScholarDigital Library
- Arvi88.Arvind, Culler, D.E., and Maa, G.K., "Assessing the Benefits of Fine-Grain Parallelism in Dataflow Programs". The International Journal of Supercomputer Applications, Vol.2, No.3, November 1988.Google Scholar
- Clar83.Clark, D.W., "Cache Performance in the VAX- 11/780". ACM Trans. Comp. Sys., Vol.1, No.l, February 1983, pp. 24-37. Google ScholarDigital Library
- Egge88.Eggers, S.J., and Katz, R.H., "A Characterization of Sharing in Parallel Programs and its Application to Coherency Protocol Evaluation". Proc. of the 15th Annual Int. Syrup. on Comp. Arch., Honolulu, Hawaii, June 1988, pp. 373-383. Google ScholarDigital Library
- Good83.Goodman, J.R., "Using Cache Memory to Reduce processor-Memory Traffic". Proc. of the l Oth Annual Int. Syrup. on Comp. Arch,, Stockholm, Sweden, 1983. Google ScholarDigital Library
- Hals88.Halstead, R.H,, Jr., and Fujita, T., "MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing". Proc. of the 15th Annual Int. Syrup. on Comp. Arch., Honolulu, Hawaii, June 1988, pp. 443-451. Google ScholarDigital Library
- Ianu88.Ianucci, R.A., "Toward a Dataflow / yon Neumann Hybrid Architecture". Proc. of the 15th Annual Int. Syrup. on Comp. Arch., Honolulu, Hawaii, June 1988, pp. 131-140. Google ScholarDigital Library
- Nikh88.Nikhil, R.S. and Ar~ind, "Can Dataflow Subsume von Neumann Computing?". Proc. of the 16th Annual Int. Syrup. on Comp. Arch., Jerusalem, Israel, June 1989. Google ScholarDigital Library
- Russ78.Russell, R.M., "The CRAY-1 Computer System". Comm. of the ACM, Vol.21, No.l, January 1978. pp. 63-72. Google ScholarDigital Library
- Saav90.Saavedra-Barrera, R.H., and Culler, D., "An Analytical Solution for a Markov Chain Modeling Multithread Execution", University of Ca/ifomia, Berkeley, technical report in preparation. Google ScholarDigital Library
- Smit82.Smith, A.J., "Cache Memories". ACM Computing Surveys, Vol. 14, No.3, September 1982, pp. 473-530. Google ScholarDigital Library
- Smit78.Smith, B.J., "A Pipelined, Shared Resource MIMD Computer". 1978 Int. Conf. on Parallel Proc., 1978, pp. 6-8.Google Scholar
- Thie89.Thiebaut, D., "On the Fractal Dimension of Computer Programs and its Application to the Prediction of the Cache Miss Ratio". IEEE Trans. on Computers, Vol,38, No.7, July 1989, pp, 1012-1026, Google ScholarDigital Library
- This88.Thistle, M.R., and Smith, B.J., "A Processor Architecture for Horizon". Supercomputing '88, Florida, October 1988, pp. 35-40. Google ScholarDigital Library
- Webe89.Weber, W., and Gupta A., "Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results". Proc. of the 16th Annual Int. Syrup. on Comp. Arch., Jerusalem, Israel, June 1989, pp. 273-280. Google ScholarDigital Library
Index Terms
- Analysis of multithreaded architectures for parallel computing
Recommendations
Reducing misspeculation penalty in trace-level speculative multithreaded architectures
ISHPC'05/ALPS'06: Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systemsTrace-Level Speculative Multithreaded Processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating on the result of several ...
Comments