ABSTRACT
Programmable circuit design has played an important role in improving design productivity over the last few decades. By imposing structure on the design, efficient automation of synthesis, placement and routing is possible. We focus on a class of programmable circuits known as mask programmable circuits. In this paper, we describe key issues in design and tool methodology that need to be addressed in creating a programmable fabric. We construct an efficient design flow that can explore different logic and routing architectures. The main advantage of our work is that we tailor tools designed for standard cell design, that are readily available in the market, to work on a programmable fabric. Our flow requires some additional software capability. A special router that understands programmable routing constructs to complete connections is described. In addition, a tool that packs logic efficiently after synthesis is also presented.
- S. Batterywala, W. Nicholls, N. Shenoy, and H. Zhou. Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing. In Proceedings of the International Conference on Computer-Aided Design, 2002.]] Google ScholarDigital Library
- V. Betz and J. Rose. VPR: A New Packing, Placement and Routing Tool for FPGA Research. In International Workshop on Field Programmable Logic and Applications, pages 213--222, 1997.]] Google ScholarDigital Library
- V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep Sub-Micron FPGAs. Kluwer Academic Publishers, 1999.]] Google ScholarDigital Library
- S. Brown, R. Francis, J. Rose, and Z. Vranesic. Field Programmable Gate Arrays. Kulwer Academic Publishers, 1992.]] Google ScholarDigital Library
- S. Brown, J. Rose, and Z. G. Vranesic. A Detailed Router for Field-Programmable Gate Arrays. In IEEE Transactions on Computer-Aided Design, pages 620--628. IEEE, May 1992.]]Google ScholarDigital Library
- Y.-W. Chang, D. F. Wong, and C. K. Wong. Universal Switch Modules for FPGA Design. In ACM Trans. on Design Automation of Electronic Systems, pages 80--101, 1996.]] Google ScholarDigital Library
- R. J. Francis, J. Rose, and K. Chung. Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. In Proceedings of the Design Automation Conference, pages 613--619, 1990.]] Google ScholarDigital Library
- H. N. Gabow. An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs. Journal of the ACM, 23:221--234, 1976.]] Google ScholarDigital Library
- S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, and R. Otten. A Novel VLSI Layout Fabric For Deep Sub-Micron Applications. In Proceedings of the Design Automation Conference, pages 491--496. IEEE/ACM, 1999.]] Google ScholarDigital Library
- G. G. F. Lemieux, S. D. Brown, and D. Vranesic. On Two-Step Routing for FPGAs. In Proceedings of the International Symposium on Physical Design, pages 60--66, 1997.]] Google ScholarDigital Library
- F. Lien, J. Feng, E. Huang, C. Sun, T. Liu, N. Liao, and D. Hightower. A Hardware/Software Solution for Embeddable FPGA. In Proceedings of the Custom Integrated Circuits Conference, pages 5.3.1--5.3.4, 2001.]]Google ScholarCross Ref
- C.-C. Lin, M. Marek-Sadowska, and D. Gatlin. On Designing Universal Logic Blocks and Their Application to FPGA Design. In IEEE Transactions on Computer-Aided Design, pages 519--527. IEEE, May 1997.]]Google Scholar
- L. McMurchie and C. Ebeling. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs. In Proceedings of ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, pages 111--117, 1995.]] Google ScholarDigital Library
- K. Mehlhorn and G. Schafer. Implementation of O (nm log n) Weighted Matchings in General Graphs. The Power of Data Structures. In Algorithm Engineering, pages 23--38, 2000.]] Google ScholarDigital Library
- F. Mo and R. K. Brayton. Fishbone: A Block-Level Placement and Routing Scheme. In Proceedings of the International Symposium on Physical Design, pages 204--209, 2003.]] Google ScholarDigital Library
- R. Murgai, N. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic Synthesis for Programmable Gate Arrays. In Proceedings of the Design Automation Conference, pages 620--625, 1990.]] Google ScholarDigital Library
- Opencores. IP Cores Repsoitory. World Wide Web, http://www.opencore.com.]]Google Scholar
- Z. Or-Bach, Z. Wurman, R. Zeman, and L. Cooke. Customizable and programmable cell array. U.S. Patent 6,331,790, Issued 18 Dec. 2001.]]Google Scholar
- C. Patel, A. Cozzi, H. Schmit, and L. Pileggi. An Architectural Exploration of Via Patterned Gate Arrays. In Proceedings of the International Symposium on Physical Design, pages 184--189, 2003.]] Google ScholarDigital Library
- L. Pileggi, H. Schmit, A. J. Strojwas, V. Kheterpal, A. Koorapaty, C. Patel, V. Rovner, and K. Y. Tong. Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off. In Proceedings of the Design Automation Conference, pages 782--787. IEEE/ACM, 2003.]] Google ScholarDigital Library
- J. Rose and S. Brown. The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays. In Proceedings of the Custom Integrated Circuits Conference, pages 27.5.1--27.5.4, 1990.]]Google ScholarCross Ref
- J. Rose, A. El Gamal, and A. Sangiovanni-Vincentelli. Architecture of Field Programmable Gate Arrays. In Proceedings of the IEEE, pages 1013--1029, 1993.]]Google ScholarCross Ref
- J. Rose, R. Francis, D. Lewis, and P. Chow. Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. In IEEE Journal of Solid-State Circuits, pages 1217--1225, 1990.]]Google Scholar
- H. Schmit and V. Chandra. FPGA Switch Block Layout and Evaluation. In Proceedings of IEEE/ACM Int. Symp. on Field Programmable Gate Arrays, pages 11--18, 2002.]] Google ScholarDigital Library
- S. Thakur and D. F. Wong. On Designing ULM-based FPGA Logic Modules. In Proceedings of ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, pages 3--9, 1995.]] Google ScholarDigital Library
- Z. Zilic and Z. G. Vranesic. Using BDDs to Design ULMs for FPGAs. In Proceedings of ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, pages 24--30, 1996.]] Google ScholarDigital Library
- P. S. Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and B. Troxel. A Hybrid ASIC and FPGA Architecture. In Proceedings of the International Conference on Computer-Aided Design, pages 187--194, 2002.]] Google ScholarDigital Library
Index Terms
- Design automation for mask programmable fabrics
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Special Section on Field Programmable Logic and Applications 2015 and Regular PapersIn this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA ...
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