skip to main content
article

A formal concurrency model based architecture description language for synthesis of software development tools

Published:11 June 2004Publication History
Skip Abstract Section

Abstract

Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of software on programmable platforms. However, in order to minimize the power and performance overhead of such processors, we are seeing the introduction of domain or application specific processors such as network and communication processors. The design of such specialized processors requires software development tools such as simulators and compilers. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description Languages (ADLs). In this paper, we present the Mescal Architecture Description Language (MADL). MADL features a two-layer structure, a core layer and an annotation layer. The core layer is based on a formal and flexible microprocessor model -- the operation state machine (OSM), which enables MADL to express the concurrency at the operation execution level for a wide range of architectures. We address the challenges faced in designing the core layer to combine the OSM model with techniques for achieving compact processor descriptions. The annotation layer features a generic syntax that allows creating annotation schemes to specify implementation dependent or tool specific information. To show the effectiveness of MADL, we present an MADL-based simulator synthesis framework that has been used to generate efficient cycle accurate simulators and instruction set simulators with very low development effort. We also describe our annotation schemes that enable the extraction of architecture properties for use in instruction scheduling and integer-linear-programming based register allocation. Our experimental results demonstrate the efficacy of MADL as a practical and promising language for the development of programmable platforms.

References

  1. H. Akaboshi. A Study on Design Support for Computer Architecture Design. PhD thesis, Department of Information Systems, Kyushu University, Japan, 1996.Google ScholarGoogle Scholar
  2. A. Appel and L. George. Optimal spilling for CISC machines with few registers. In Proceedings of the Conference on Programming Language Design and Implementation, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. IEEE Computer, pages 59--67, Feb 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. A. Fauth, J. V. Praet, and M. Freericks. Describing instructions set processors using nML. In Proceedings of Conference on Design Automation and Test in Europe, pages 503--507, Paris, France, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. R. Fourer, D. Gay, and B. Kernighan. AMPL: A Modeling Language for Mathematical Programming. Duxbury Press, 2002.Google ScholarGoogle Scholar
  6. Fujitsu Limited. Hiperion II - Digital Signal Processor User's Manual, 1998.Google ScholarGoogle Scholar
  7. G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An instruction set description language for retargetability. In Proceedings of Design Automation Conference, pages 299--302, June 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In Proceedings of Conference on Design Automation and Test in Europe, pages 485--490, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In International Symposium on Microarchitecture, pages 330--335, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. R. B. Lee and A. M. Fiskiran. PLX: A fully subword-parallel instruction set architecture for fast scalable multimedia processing. In Proceedings of the 2002 IEEE International Conference on Multimedia and Expo (ICME 2002), pages 117--120, August 2002.Google ScholarGoogle ScholarCross RefCross Ref
  11. P. Mishra, N. Dutt, and A. Nicolau. Functional abstraction driven design space exploration of heterogeneous programmable architectures. In Proceedings of the International Symposium on System Synthesis, Oct 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr. LISA -- machine description language for cycle-accurate models of programmable DSP architectures. In Proceedings of Design Automation Conference, pages 933--938, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. W. Qin. http://www.ee.princeton.edu/MESCAL/madl.html, 2004.Google ScholarGoogle Scholar
  14. W. Qin and S. Malik. Flexible and formal modeling of microprocessors with application to retargetable simulation. In Proceedings of Conference on Design Automation and Test in Europe, pages 556--561, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. S. Rajagopalan, M. Vacharajani, and S. Malik. Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Target Compiler Technologies N.V. http://www.retraget.com, 2004.Google ScholarGoogle Scholar
  17. O. Wahlen, M. Hohenauer, and R. Leupers. Instruction scheduler generation for retargetable compilation. IEEE Design & Test of Computers, 20(1):34--41, Jan 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. G. Zimmerman. The MIMOLA design system: A computer-aided processor design method. In Proceedings of Design Automation Conference, pages 53--58, June 1979. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. A formal concurrency model based architecture description language for synthesis of software development tools

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 39, Issue 7
        LCTES '04
        July 2004
        265 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/998300
        Issue’s Table of Contents
        • cover image ACM Conferences
          LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
          June 2004
          276 pages
          ISBN:1581138067
          DOI:10.1145/997163

        Copyright © 2004 ACM

        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 11 June 2004

        Check for updates

        Qualifiers

        • article

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader