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FORMLESS: scalable utilization of embedded manycores in streaming applications

Published:12 June 2012Publication History

ABSTRACT

Variants of dataflow specification models are widely used to synthesize streaming applications for distributed-memory parallel processors. We argue that current practice of specifying streaming applications using rigid dataflow models, implicitly prohibits a number of platform oriented optimizations and hence limits portability and scalability with respect to number of processors. We motivate Functionally-cOnsistent stRucturally-MalLEabe Streaming Specification, dubbed FORMLESS, which refers to raising the abstraction level beyond fixed-structure dataflow to address its portability and scalability limitations. To demonstrate the potential of the idea, we develop a design space exploration scheme to customize the application specification to better fit the target platform. Experiments with several common streaming case studies demonstrate improved portability and scalability over conventional dataflow specification models, and confirm the effectiveness of our approach.

References

  1. S. Battacharyya, E. Lee, and P. Murthy. Software synthesis from dataflow graphs. Kluwer Academic Publishers, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. S. Stuijk, M. Geilen, and T. Basten. Throughput-buffering trade-off exploration for cyclo-static and synchronous dataflow graphs. IEEE Transactions on Computers, 57(10):1331--1345, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. M. Gordon. Compiler techniques for scalable performance of stream programs on multicore architectures. PhD thesis, Massachusetts Institute of Technology, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Andy D. Pimentel et al. Exploring embedded-systems architectures with Artemis. IEEE Computer, 34(11):57--63, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. A. Sangiovanni-Vincentelli et al. Benefits and challenges for platform-based design. Design Automation Conference (DAC), pages 409--414, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. D. Truong et al. A 167--processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling. Symposium on VLSI Circuits, 2008.Google ScholarGoogle Scholar
  7. S. Bell et al. TILE64 processor: A 64-core SoC with mesh interconnect. International Solid-State Circuits Conference (ISSCC), 2008.Google ScholarGoogle Scholar
  8. E. Lee and D. Messerschmitt. Synchronous data flow. Proceedings of the IEEE, 75(9):1235--1245, 1987.Google ScholarGoogle ScholarCross RefCross Ref
  9. M. Geilen and T. Basten. Reactive process networks. International Conference on Embedded Software (EMSOFT), pages 137--146, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. J. Colaço, A. Girault, G. Hamon, and M. Pouzet. Towards a higher-order synchronous data-flow language. International Conference on Embedded Software (EMSOFT), pages 230--239, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. W. Taha. A gentle introduction to multi-stage programming. Domain-Specific Program Generation, Lecture Notes in Computer Science (LNCS), 2004.Google ScholarGoogle Scholar
  12. J. Adam Cataldo. The power of higher-order composition languages in system design. PhD thesis, University of California, Berkeley, 2006.Google ScholarGoogle Scholar
  13. Marc Geilen. Reduction techniques for synchronous dataflow graphs. Design Automation Conference (DAC), 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. B. Bhattacharya and S. Bhattacharyya. Parameterized dataflow modeling for DSP systems. IEEE Transactions on Signal Processing, 49(10):2408--2421, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. B.D. Theelen et al. A scenario-aware data flow model for combined long-run average and worst-case performance analysis. Formal Methods and Models in CoDesign, 2006.Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Maarten H. Wiggers, Marco J. G. Bekooij, and Gerard J. M. Smit. Buffer capacity computation for throughput constrained streaming applications with data-dependent inter-task communication. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Pascal Fradet, Alain Girault, and Peter Poplavko. A schedulable parametric data-flow MoC. Design, Automation, and Test in Europe (DATE), 2012.Google ScholarGoogle Scholar
  18. J. Nickolls et al. Scalable parallel programming with CUDA. ACM Queue, 6:40--53, March 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. CUDA C best practices guide, chapter 4.4. March 2011.Google ScholarGoogle Scholar
  20. G. Karypis and V. Kumar. METIS 4.0: Unstructured graph partitioning and sparse matrix ordering system. Technical report, CS Dept., University of Minnesota, Minneapolis, 1998.Google ScholarGoogle Scholar
  21. T. Mohsenin, D. Truong, and B. Baas. Multi-split-row threshold decoding implementations for LDPC codes. International Symposium on Circuits and Systems (ISCAS), 2009.Google ScholarGoogle ScholarCross RefCross Ref
  22. Po-Kuan Huang, Matin Hashemi, and Soheil Ghiasi. System-level performance estimation for application-specific mpsoc interconnect synthesis. Symposium on Application Specific Processors (SASP), 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Matin Hashemi. Automated Software Synthesis for Streaming Applications on Embedded Manycore Processors. PhD thesis, University of California, Davis, 2011. Chapter 4. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  • Published in

    cover image ACM Conferences
    LCTES '12: Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
    June 2012
    153 pages
    ISBN:9781450312127
    DOI:10.1145/2248418
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 47, Issue 5
      LCTES '12
      MAY 2012
      152 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2345141
      Issue’s Table of Contents

    Copyright © 2012 ACM

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    Publication History

    • Published: 12 June 2012

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