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Parallel copy motion
Recent results on the static single assignment (SSA) form open promising directions for the design of register allocation heuristics for just-in-time (JIT) compilation. In particular, tree-scan allocators with two decoupled phases, one for spilling and ...
B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems
High performance embedded processors are equipped with the Translation Look-aside Buffer (TLB) which forms the key ingredient to efficient and speedy virtual memory management. The TLB though small, is frequently accessed, and therefore not only ...
Interval analysis of microcontroller code using abstract interpretation of hardware and software
Static analysis is often performed on source code where intervals -- possibly the most widely used numeric abstract domain -- have successfully been used as a program abstraction for decades. Binary code on microcontroller platforms, however, is ...
A compiler-based infrastructure for fault-tolerant co-design
- Felipe Restrepo-Calle,
- Antonio Martínez-Álvarez,
- Hipólito Guzmán-Miranda,
- F. R. Palomo,
- M. A. Aguirre,
- Sergio Cuenca-Asensi
The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault ...
Workload characterization supporting the development of domain-specific compiler optimizations using decision trees for data mining
Embedded systems have successfully entered a broad variety of application domains such as automotive and industrial control, telecommunications, networking, digital media, consumer equipment, office automation and many more. In this paper we investigate ...
Modeling shared cache and bus in multi-cores for timing analysis
Timing analysis of concurrent programs running on multi-core platforms is currently an important problem. The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus. In this ...
A higher-order extension for imperative synchronous languages
This article presents the very first effective design of higher-order modules in the synchronous programming language Esterel. Higher-order modules, together with the robust separate compilation scheme that implements it, allow us to address a yet ...
Supporting islands of coherency for highly-parallel embedded architectures using compile-time virtualisation
As their complexity grows, the architectures of embedded systems are becoming increasingly parallel. However, the frameworks used to assist development on highly-parallel general-purpose systems (such as CORBA or MPI) are too heavyweight for use on the ...
System level MPSoC design: a bright future for compiler technology?
Looking back at the SCOPES history, compiler research for embedded processors started out in the 1990s with two major ambitions: (1) more architecture aware code optimizations to better support specialized target machines such as DSPs, and (2) higher ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
SCOPES '21 | 15 | 7 | 47% |
SCOPES '20 | 13 | 8 | 62% |
SCOPES '17 | 9 | 6 | 67% |
M-SCOPES '13 | 16 | 9 | 56% |
SCOPES '09 | 26 | 8 | 31% |
Overall | 79 | 38 | 48% |