DAC

This paper presents a new logic simulation technique that uses software levelized compiled-code (LCC) for synchronous designs. Three approaches are proposed: C source code, target machine code and interpreted code. The evaluation speed for the software ...

The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the ...

This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE ...

An improved systematic method is introduced which reduces the number of ad hoc steps and provides all possible systolic solutions for a given algorithm. Algorithms are modeled using index space (geometric) representations where the index transformation ...

In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined designs. The model includes prediction of the number of operators, registers and multiplexers from a behavioral specification. It has been verified with ...

An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in ...

This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The ...

Simulated annealing is a powerful optimization technique based on the annealing phenomenon in crystallization. In this paper we propose a simulated sintering technique which is analogous to the sintering process in material processing. In sintering one ...

ESP (Evolution-based Standard cell Placement) is a new program package designed to perform standard cell placement and includes macro-block placement capabilities. It uses the new heuristic method of simulating an evolutionary process in order to ...

This paper, primarily, presents the facilities that satisfy the user requirements for a modern software engineering environment under development on VS at Wang Laboratories, Inc. Requirements analysis is emphasized as a cornerstone for the future ...

This paper is about the software engineering facets of the making of a large programming systems product for symbolic VLSI CAD called VIVID. Issues such as how teams were organized, how conceptual integrity was maintained, and portability are discussed. ...

Philips Laboratories has developed HVDEV, a procedural language layout generator for compiling high voltage MOS device layouts from behavioral specifications. HVDEV is analyzed as a case study in silicon compilation software engineering. The paper ...

A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience ...

The HSS is a Hardware Switch level Simulator that has been designed and built to be a useful and cost effective addition to a MOS circuit designers tool set. The HSS is based on the MOSSIM software simulator, but has been further developed to include ...

MARS (Microprogrammable Accelerator for Rapid Simulations) is a multiprocessor based hardware accelerator capable of efficiently implementing a wide range of computationally complex algorithms. Its architecture is ideally suited for performing event ...

Accurate circuit simulation is a very important step in the design of high performance integrated circuits. The ever increasing size of integrated circuits requires the use of an inordinate amount of computer time to be spent in circuit simulation. ...

This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in ...

The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are ...

Several methods for increasing the speed of combinational static CMOS circuits, including techniques for partitioning gates on the basis of circuit complexity and input arrival time, are described. The target layout style is standard cell, rather than a ...

This paper develops equations that can extend the performance of high speed digital systems. The equations allow the application of timing analysis to the selection of the minimum series terminating resistor. Use of the minimum terminating resistor ...

A channel router which is to be effective for general-purpose automatic routing must be able to use different sets of routing criteria priorities, in a controllable manner. We present an approach to channel routing with compaction in which channel ...

This paper presents a channel router that is designed to handle channels having irregularly-spaced terminals on different layers. The development of this router has investigated combining several basic wiring functions in distinct stages to achieve the ...

The concept of L-shaped channels was first introduced in RRDO [1] to generate a feasible routing order for nonslicing-structure placement in building-block layout design. This paper presents two approaches for the L-shaped channel-routing problem. In ...

This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias. The time complexity of the algorithm is Ο(n³) where n is the number of routing segments in the given ...

The term logic synthesis is used to describe systems that range from relatively simple mapping schemes to tools with sophisticated logic optimizations. In this tutorial, the requirements on logic synthesis systems will be discussed and the advantages ...

Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the ...

A new digital simulation algorithm is presented based on the concept of demand driven simulation. Where traditional event driven simulation propagates signal values forward through a circuit in response to input pin events, demand driven simulation ...

Architectural simulation of complex systems is usually constrained by available computational resources. Recently, several commercial parallel processing systems have appeared with price-performance levels that make very intense simulations affordable. ...

The HAL system performs data path synthesis using a new scheduling algorithm that is part of an interdependent scheduling and allocation scheme. This scheme uses an estimate of the hardware allocation to guide and optimize the scheduling subtask. The ...

This paper describes the principles and implementation of design-process control in a micro-architecture compiler. The knowledge-base relies on both local and global evaluations to determine strategies to achieve global goals and then implements those ...