Stefan Kraemer
ABSTRACT
Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7x to 72x can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%.
- A. V. Aho, M. S. Lam, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools (2nd Edition). Addison Wesley, August 2006. Google Scholar
Digital Library
- G. Bronevetsky, D. Marques, K. Pingali, and P. Stodghill. Automated Application-Level Checkpointing of MPI Programs. In PPoPP '03: Principles and Practice of Parallel Programming, New York, NY, USA, 2003. ACM Press. Google ScholarDigital Library
- G. Bronevetsky, D. Marques, K. Pingali, and P. Stodghill. Collective Operations in Application-Level Fault-Tolerant MPI. In ICS '03: Proceedings of the 17th annual International Conference on Supercomputing, New York, NY, USA, 2003. ACM Press. Google ScholarDigital Library
- L. Gao, S. Kraemer, R. Leupers, G. Ascheid, and H. Meyr. A Fast and Generic Hybrid Simulation Approach Using C Virtual Machine. In CASES '07: Compilers, Architecture and Synthesis for Embedded Systems, New York, NY, USA, 2007. ACM Press. Google ScholarDigital Library
- IEEE Standards Committee 754. IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Standard 754-1985. Institute of Electrical and Electronics Engineers, New York, 1985. Reprinted in ACM SIGPLAN Notices, 22(2):9--25, 1987.Google Scholar
- A. A. Jerraya, A. Bouchhima, and F. Pétrot. Programming Models and HW-SW Interfaces Abstraction for Multi-Processor SoC. In DAC '06: Conference on Design Automation, New York, NY, USA, 2006. ACM Press. Google ScholarDigital Library
- Karuri, K., Al Faruque, M.A., Kraemer, S., Leupers, R., Ascheid, G. and Meyr, H. Fine-grained Application Source Code Profiling for ASIP Design. In 42nd Design Automation Conference, Anaheim, California, USA, June 2005. Google ScholarDigital Library
- T. Kempf, K. Karuri, S. Wallentowitz, G. Ascheid, R. Leupers, and H. Meyr. A SW Performance Estimation Framework for Early System-Level-Design using Fine-Grained Instrumentation. In DATE '06: Conference on Design, Automation and Test in Europe, 3001 Leuven, Belgium, Belgium, 2006. European Design and Automation Association. Google ScholarDigital Library
- B. W. Kernighan and D. Ritchie. The C Programming Language (2nd Edition). Prentice Hall PTR, March 1988. Google ScholarDigital Library
- A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, and A. Hoffmann. A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation. In DAC '02: Conference on Design automation, New York, NY, USA, 2002. ACM Press. Google ScholarDigital Library
- M. Poncino and J. Zhu. DynamoSim: A Trace-based Dynamically Compiled Instruction Set Simulator. In ICCAD'04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, Washington, DC, USA, 2004. IEEE Computer Society. Google ScholarDigital Library
- W. Qin, J. D'Errico, and X. Zhu. A Multiprocessing Approach to Accelerate Retargetable and Portable Dynamic-compiled Instruction-set Simulation. In CODES+ISSS '06: Conference on Hardware/Software Codesign and System Synthesis, New York, NY, USA, 2006. ACM Press. Google ScholarDigital Library
- M. Reshadi, P. Mishra, and N. Dutt. Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation. In DAC '03: Conference on Design Automation, New York, NY, USA, 2003. ACM Press. Google ScholarDigital Library
- J. Ringenberg, C. Pelosi, D. Oehmke, and T. Mudge. Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification. Performance Analysis of Systems and Software, March 2005. Google ScholarDigital Library
- T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically Characterizing Large Scale Program Behavior. In ASPLOS-X: Proceedings of the 10th international conference on Architectural Support for Programming Languages and Operating Systems, New York, NY, USA, 2002. ACM Press. Google ScholarDigital Library
- T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder. Discovering and Exploiting Program Phases. IEEE Micro, December 2003. Google ScholarDigital Library
- P. K. Szwed, D. Marques, R. M. Buels, S. A. McKee, and M. Schulz. SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing. interact, 00, 2004.Google Scholar
- R. Wunderlich, T. Wenisch, B. Falsafi, and J. Hoe. SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. In 30th Annual International Symposium on Computer Architecture, June 2003. Google ScholarDigital Library
- J. J. Yi and D. J. Lilja. Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations. IEEE Trans. Comput., 55(3), 2006. Google ScholarDigital Library
- S. Yoo, I. Bacivarov, A. Bouchhima, Y. Paviot, and A. A. Jerraya. Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. In DATE '03: Conference on Design, Automation and Test in Europe, Washington, DC, USA, 2003. IEEE Computer Society. Google ScholarDigital Library
Index Terms
- HySim: a fast simulation framework for embedded software development
Recommendations
Synchronization for hybrid MPSoC full-system simulation
DAC '12: Proceedings of the 49th Annual Design Automation ConferenceFull-system simulators are essential to enable early software development and increase the MPSoC programming productivity, however, their speed is limited by the speed of processor models. Although hybrid processor simulators provide native execution ...
Multiprocessor performance estimation using hybrid simulation
DAC '08: Proceedings of the 45th annual Design Automation ConferenceWith the growing number of programmable processing elements in today's Multi Processor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware architecture and the software running on them is also increasing. In MPSoC ...
Hybrid Simulation for Energy Estimation of Embedded Software
Software energy estimation is a critical step in the design of energy-efficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slow for iterative use in system-level exploration and for embedded systems ...
Comments