ABSTRACT
Software accounts for more than 80% of embedded system development efforts, so software performance estimation is a very important issue in system design. Recently, source level simulation (SLS) has become a state-of-the-art approach for software simulation in system level design. However, the simulation accuracy relies on the mapping between source code and binary code, which can be destroyed by compiler optimizations. This drawback strongly limits the usability of this technique in practical system design. We introduce an approach to overcome this limitation by converting source code to a low level representation, called intermediate source code (ISC). ISC has accounted for most compiler optimizations and has a structure close to binary code, so it allows for accurate back-annotation of timing information from the binary level. To show the benefits of our approach, we present a quantitative comparison of the related techniques with the proposed one, using a set of benchmarks.
- J. R. Bammi, W. Kruijtzer, L. Lavagno, E. Harcourt, and M. Lazarescu. Software performance estimation strategies in a system-level design tool. In Proceedings of the International Workshop on HW/SW Codesign, 2000. Google ScholarDigital Library
- E. Cheung, H. Hsieh, and F. Balarin. Framework for fast and accurate performance simulation of multiprocessor systems. In Proceedings of IEEE International Workshop on High Level Design Validation and Test, 2007. Google ScholarDigital Library
- M.-K. Chung, S. Yang, S.-H. Lee, and C.-M. Kyung. System-level HW/SW co-simulation framework for multiprocessor and multithread SoC. In Proceedings of IEEE VLSI-TSA international symposium on VLSI Design, Automation and Test, 2005.Google Scholar
- F. Fummi, G. Perbellini, M. Loghi, and M. Poncino. ISS-centric modular HW/SW co-simulation. In Proceedings of the ACM Great Lakes symposium on VLSI, 2006. Google ScholarDigital Library
- P. Giusto, G. Martin, and E. Harcourt. Reliable estimation of execution time of embedded software. In Proceedings of the conference on Design, Automation and Test in Europe, 2001. Google ScholarDigital Library
- T. Kempf, K. Karuri, S. Wallentowitz, G. Ascheid, R. Leupers, and H. Meyr. A SW performance estimation framework for early system-level-design using fine-grained instrumentation. In Proceedings of the conference on Design, Automation and Test in Europe, 2006. Google ScholarDigital Library
- M. Lazarescu, M. Lajolo, J. Bammi, E. Harcourt, and L. Lavagno. Compilation-based software performance estimation for system level design. In Proceedings of the International Workshop on HW/SW Codesign, 2000.Google ScholarCross Ref
- J.-Y. Lee and I.-C. Park. Timed compiled-code simulation of embedded software for performance analysis of SOC design. In Proceedings of the Design Automation Conference, 2002. Google ScholarDigital Library
- T. Meyerowitz, M. Sauermann, D. Langen, and A. Sangiovanni-Vincentelli. Source-level timing annotation and simulation for a heterogeneous multiprocessor. In Proceedings of the conference on Design, Automation and Test in Europe, 2008. Google ScholarDigital Library
- T. Nakada, T. Tsumura, and H. Nakashima. Design and implementation of a workload specific simulator. In Proceedings of the annual Symposium on Simulation, 2006. Google ScholarDigital Library
- J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. High-performance timing simulation of embedded software. In Proceedings of the Design Automation Conference, 2008. Google ScholarDigital Library
- Z. Wang, A. Sanchez, and A. Herkersdorf. Scisim: A software performance estimation framework using source code instrumentation. In Proceedings of the International Workshop on Software and Performance, 2008. Google ScholarDigital Library
- V. Zivojnovic and H. Meyr. Compiled HW/SW co-simulation. In Proceedings of the Design Automation Conference, 1996. Google ScholarDigital Library
Index Terms
- An efficient approach for system-level timing simulation of compiler-optimized embedded software
Recommendations
Fast and accurate source-level simulation of software timing considering complex code optimizations
DAC '11: Proceedings of the 48th Design Automation ConferenceThis paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components ...
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12: Proceedings of the Conference on Design, Automation and Test in EuropeSource code instrumentation is a widely used method to generate fast software simulation models by annotating timing information into application source code. Source-level simulation models can be easily integrated into SystemC based simulation ...
A Mixed Timing System-Level Embedded Software Modelling and Simulation Approach
ICESS '09: Proceedings of the 2009 International Conference on Embedded Software and SystemsSystem-level software modeling and simulation have become important techniques for real-time embedded system early design space exploration. However, the timing accuracy issues have not been solved well in current methods, which produce unrealistic ...
Comments