ABSTRACT
Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently. Most existing DVFS approaches are profile-based offline schemes which are mainly suitable for applications whose execution char-acteristics are constrained and repeatable. While some work has been published about online DVFS schemes, the prior approaches are typically heuristic-based. In this paper, we present an effective online DVFS scheme for an MCD processor which takes a formal analytic approach, is driven by dynamic workloads, and is suitable for all applications. In our approach, we model an MCD processor as a queue-domain network and the online DVFS as a feedback control problem with issue queue occupancies as feedback signals. A dynamic stochastic queuing model is first proposed and linearized through an accu-rate linearization technique. A controller is then designed and verified by stability analysis. Finally we evaluate our DVFS scheme through a cycle-accurate simulation with a broad set of applications selected from MediaBench and SPEC2000 benchmark suites. Compared to the best-known prior approach, which is heuristic-based, the proposed online DVFS scheme is substantially more effective due to its automatic regulation ability. For example, we have achieved a 2-3 fold increase in efficiency in terms of energy-delay product improvement. In addition, our control theoretic technique is more resilient, requires less tuning effort, and has better scalability as compared to prior online DVFS schemes.We believe that the techniques and methodology described in this paper can be generalized for energy control in processors other than MCD, such as tiled stream processors.
- Carl Anderson. Tuning and optimization of a 170m transistor microprocessor. In Proceedings of the IEEE/ACM International Workshop on Timing Issue in the Specification and Synthesis of Digital System (TAU2000), Dec 2000.Google Scholar
- K.J. Astrom and B. Wittenmark. Adaptive Control. Addison-Wesley, 1995. Google ScholarDigital Library
- S. K. Bose. An Introduction to Queueing Systems. Kluwer Academic, 2002.Google ScholarCross Ref
- D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimization. In Proc. of the ISCA-27, June 2000. Google ScholarDigital Library
- D. Burger and T. M. Austin. The SimpleScalar tool set version 2.0. Technical Report 97--1342, Department of Computer Science, University of Wisconsin-Madison, June 1997.Google ScholarDigital Library
- T. Chelcea and S. M. Nowick. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proc. of DAC-2001, pages 21--26, 2001. Google ScholarDigital Library
- L.T. Clark. Circuit design of XScale microprocessors. In Proceedings of the 2001 Symposium on VLSI Circuits, June 2001.Google Scholar
- M. Taylor et al. The RAW processor - a scalable 32-bit fabric for embedded and general purpose computing. In Proceedings of Hot Chips XIII, August 2001.Google Scholar
- R.V. Hogg and A.T. Craig. Introduction to Mathematical Statistics, Fifth edition. Prentice Hall, 1995.Google Scholar
- C-H Hsu and U. Kremer. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction. In Proc. of PLDI-2003, pages 38--48, June 2003. Google ScholarDigital Library
- A. Iyer and D. Marculescu. Power efficiency of multiple clock multiple voltage cores. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2002. Google ScholarDigital Library
- A. Iyer and D. Marculescu. Power-performance evaluation of globally asynchronous, locally synchronous processors. In Proc. of the 26th ISCA, May 2002. Google ScholarDigital Library
- K. Choi, R. Soma, and M. Pedram. Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times. In Proceedings of DATE, Feb 2004. Google ScholarDigital Library
- B.C. Kuo. Automatic Control Systems., 7th edition. Prentice Hall, 1995. Google ScholarDigital Library
- D.V. Lindley. The theory of queues with a single server. In Proceedings of the Cambridge Philosophical Society, pages 277--289, 1952.Google ScholarCross Ref
- J. R. Lorch and A. J. Smith. Improving dynamic voltage scaling algorithm with PACE. In Proceedings of the SIGMETRICS-2001, pages 50--61, June 2001. Google ScholarDigital Library
- Z. Lu, J.Hein, M. Stan, J. Lach, and K. Skadron. Control-theoretic dynamic frequency and voltage scaling. In Proc. of the Intl. Conference on Compiler, Architecture, and Synchesis for Embedded Systems (CASES), October 2002. Google ScholarDigital Library
- G. Magklis, M.L. Scott, G. Semeraro, D.H. Albonesi, and S.Dropsho. Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In Proc. of the 30th ISCA, June 2003. Google ScholarDigital Library
- D. Marculescu. On the use of microarchitecture-driven dynamic voltage scaling. In In Workshop on Complexity Effective Design, Vancouver, Canada, June 2000., June 2000.Google Scholar
- D. Marculescu, D.H. Albonesi, A. Buyuktosunoglu, and P. Bose. Partially asynchronous microprocessors (PAMs). In ISCA 2003 Tutorial, June 2003.Google Scholar
- D. Matzke. Will physical scalability sabotage performance gains? IEEE Computer, pages 37--39, Sep 1997. Google ScholarDigital Library
- E. Perelman, G. Hamerly, and B. Calder. Picking statistically valid and early simulation points. In Proc. of the PACT-2003, September 2003. Google ScholarDigital Library
- G. Semeraro, D.H. Albonesi, S.G. Dropsho, G. Magklis, S. Dwarkadas, and M.L. Scott. Dynamic frequency and voltage control for a multiple clock domain microarchitecture. In Proc. of the 35th Micro, pages 356--367, November 2002. Google ScholarDigital Library
- G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M.L. Scott. Energy efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In Proc. of the 8th HPCA, pages 29--40, February 2002. Google ScholarDigital Library
- G. Semeraro, G. Magklis, and Y. Zhu. Personal communications. December 2003.Google Scholar
- A.E. Sjogren and C.J. Myers. Interfacing synchronous and asynchronous modules within a high-speeed pipeline. In Proceedings of the 17th International Conference on Advanced Research in VLSI, pages 47--61, Sept 1997. Google ScholarDigital Library
- K. Skadron, T. Abdelzaher, and M. Stan. Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management. In Proc. of the 8th HPCA, February 2002. Google ScholarDigital Library
- Fen Xie, Margaret Martonosi, and Sharad Malik. Compile-time dynamic voltage scaling settings: Opportunities and limits. In Proc. of 2003 PLDI, June 2003. Google ScholarDigital Library
- K.Y. Yun and A. E. Dooply. Pausible clocking based heterogeneous systems. IEEE Transactions on VLSI Systems, 7(4):482--487, December 1999. Google ScholarDigital Library
Index Terms
- Formal online methods for voltage/frequency control in multiple clock domain microprocessors
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Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS '04Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain ...
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS 2004Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain ...
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS '04Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain ...
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