ABSTRACT
This paper attempts to reconcile the growing interdependency between nanometer lithography and physical design. We first introduce the concept of lithography hotspots and the edge placement error (EPE) map to measure the overall printability and manufacturing effort. We then adapt fast lithography simulation models to generate EPE map. Guided by EPE map, we develop effective RET-aware detailed routing (RADAR) techniques that can handle full-chip capacity to enhance the overall printability while maintaining other design closure. RADAR is implemented in an industry strength detailed router, and tested using some 65nm designs. Our experimental results show that we can achieve up to 40% EPE reduction with reasonable CPU time.
- L. W. Liebmann, "Layout impact of resolution enhancement techniques: impediment or opportunity?", Int. Symp. on Physical Design, 2003. Google ScholarDigital Library
- F. M. Schellenberg, "Resolution enhancement technology: the past, the present and extension for the future". SPIE Microlithography Symposium, 2004.Google Scholar
- P. Gupta and A. B. Kahng, "Manufacturing-aware physical design," ICCAD, pp. 681--687, 2003. Google ScholarDigital Library
- H. K.-S. Leung, "Advanced routing in changing technology landscape," Int. Symp. on Physical Design, pp. 118--121, 2003. Google ScholarDigital Library
- A. B. Kahng, "Research directions for coevolution of rules and routers," in Proc. Int. Symp. on Physical Design, pp. 122--125, 2003. Google ScholarDigital Library
- L. Scheffer, "Physical CAD changes to incorporate design for lithography and manufacturability," ASPDAC, Jan. 2004. Google ScholarDigital Library
- M. Lavin, F.-K. Luen, and G. Northrop, "Backend CAD flows for 'Restrictive Design Rules'", ICCAD, 2004. Google ScholarDigital Library
- PROLITH (version 8.0), KLA-Tencor Corporation.Google Scholar
- SOLID-CTM (version 6.4.1), Sigma-C Software.Google Scholar
- L.-D. Huang and D. F. Wong, "Optical proximity correction (OPC)-friendly maze routing," DAC, 2004. Google ScholarDigital Library
- Y.C. Pati, A.A. Ghazanfarian, and R.F. Pease, "Exploiting structure in fast aerial image computation for IC patterns", IEEE Trans. Semi. Mfg., Feb 1997.Google ScholarCross Ref
- J. Stirniman and M. Rieger, "Fast proximity correction with zone sampling", in Proc. SPIE Symposium on Microlithography, vol. 2197, pp 294--301, 1994.Google Scholar
- N. B. Cobb, Fast Optical and process Proximity Correction Algorithms for Integrated Circuit Manufacturing, Ph.D. Thesis, UC Berkeley, 1998. Google ScholarDigital Library
- Blast-Fusion, Magma Design Automation.Google Scholar
Index Terms
- RADAR: RET-aware detailed routing using fast lithography simulations
Recommendations
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
DAC '08: Proceedings of the 45th annual Design Automation ConferenceIn this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed ...
Predictive formulae for OPC with applications to lithography-friendly routing
DAC '08: Proceedings of the 45th annual Design Automation ConferenceDue to the sub-wavelength lithography, manufacturing sub-90 nm feature sizes require intensive use of resolution-enhancement techniques, among which optical proximity correction (OPC) is the most popular technique in industry. Considering the OPC ...
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
DAC '03: Proceedings of the 40th annual Design Automation ConferenceAs minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (...
Comments