Jingcao Hu
ABSTRACT
In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. At the same time, the performance of the mapped system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy-aware mapping, in a topological sense, and then propose an efficient branch-and-bound algorithm to solve it. Experimental results show that the proposed algorithm is very fast and robust, and significant energy savings can be achieved. For instance, for a complex video/audio SoC design, on average, 60.4% energy savings have been observed compared to an ad-hoc implementation.
- P. Guerrier, A. Greiner, "A generic architecture for on-chip packet-switched interconnections," Proc. DATE, pp. 250--256, March 2000. Google Scholar
Digital Library
- W. J. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks," Proc. DAC, pp. 684--689, June 2001. Google ScholarDigital Library
- J. Chang, M. Pedram, "Codex-dp: co-design of communicating systems using dynamic programming," IEEE Tran. on CAD of Integrated Circuits and Systems, vol. 19, No. 7, July 2002. Google ScholarDigital Library
- A. Hemani, et al, "Network on a chip: an architecture for billion transistor era," Proc. of the IEEE NorChip Conf., Nov. 2000.Google Scholar
- S. Kumar, et al, "A network on chip architecture and design methodology," Proc. Symposium on VLSI, pp. 117--124, April 2002. Google ScholarDigital Library
- C. J. Glass and L. M. Ni, "The turn model for adaptive routing," Proc. ISCA, May 1992. Google ScholarDigital Library
- T. T. Ye, L. Benini, G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," Proc. DAC, June 2002. Google ScholarDigital Library
- R. P. Dick, D. L. Rhodes, W. Wolf, "TGFF: task graphs for free," Proc. Intl. Workshop on Hardware/Software Codesign, March 1998. Google ScholarDigital Library
- M. R. Garey, D. S. Johnson, "Computers and intractability: a guide to the theory of NP-completeness," Freeman, 1979. Google ScholarDigital Library
- http://www.mentor.com/inventra/cores/catalog/index.htmlGoogle Scholar
Recommendations
Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures
Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient ...
Energy- and performance-aware mapping for regular NoC architectures
In this paper, we present an algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total ...
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture
NoCArc '10: Proceedings of the Third International Workshop on Network on Chip ArchitecturesMapping Intellectual Property (IP) cores onto a Network-on-Chip (NoC) architecture is an important phase of NoC design and the performance and energy consumption of the chip are the major issues that affect the design. In this paper, we analyze the ...
Comments