Yaoyao Ye
Jiang Xu
Skip Abstract Section
Abstract
Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC.
- Anan, T., Suzuki, N., Yashiki, K., Fukatsu, K., Hatakeyama, H., Akagawa, T., Tokutome, K., and Tsuji, M. 2008. High-speed 1.1-um-range InGaAs VCSELs. In Proceedings of the Optical Fiber Communication/National Fiber Optic Engineers Conference. 1--3.Google Scholar
- Artundo, I., Heirman, W., Loperena, M., Debaes, C., Van Campenhout, J., and Thienpont, H. 2009. Low-power reconfigurable network architecture for on-chip photonic interconnects. In Proceedings of the 17th IEEE Symposium on High Performance Interconnects (HOTI). 163--169. Google ScholarDigital Library
- Bahirat, S. and Pasricha, S. 2009. Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. In Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). 129--136. Google ScholarDigital Library
- Bahirat, S. and Pasricha, S. 2010. UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications. In Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED). 721--729.Google Scholar
- Balfour, J. and Dally, W. J. 2006. Design tradeoffs for tiled CMP on-chip networks. In Proceedings of the 20th Annual International Conference on Supercomputing (ICS). 187--198. Google ScholarDigital Library
- Batten, C., Josh, A., Orcutt, J., Khilo, A., Moss, B., Holzwarth, C., Popovic, M., Li, H., Smith, H., Hoyt, J., Kartner, F., Ram, R., Stojanovic, V., and Asanovic, K. 2008. Building manycore processor-to-DRAM networks with monolithic silicon photonics. In Proceedings of the 16th IEEE Symposium on High Performance Interconnects (HOTI). 21--30. Google ScholarDigital Library
- Benini, L. and De Micheli, G. 2001. Powering networks on chips. In Proceedings of 14th International Symposium on System Synthesis (ISSS). 33--38. Google ScholarDigital Library
- Benini, L. and De Micheli, G. 2002. Networks on chip: A new paradigm for systems on chip design. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE). 418--419. Google ScholarDigital Library
- Biberman, A., Lee, B., Sherwood-Droz, N., Lipson, M., and Bergman, K. 2010. Broadband operation of nanophotonic router for silicon photonic networks-on-chip. IEEE Photon. Technol. Lett. PP 99, 1--1.Google Scholar
- Bjerregaard, T. and Mahadevan, S. 2006. A survey of research and practices of network-on-chip. ACM Comput. Surv. 38, 1, 1. Google ScholarDigital Library
- Bonetto, E., Chiaraviglio, L., Cuda, D., Gavilanes Castillo, G., and Neri, F. 2009. Optical technologies can improve the energy efficiency of networks. In Proceedings of the 35th European Conference on Optical Communication (ECOC). 1--4.Google Scholar
- Briere, M., Girodias, B., Bouchebaba, Y., Nicolescu, G., Mieyeville, F., Gaffiot, F., and O’Connor, I. 2007. System level assessment of an optical NoC in an MPSoC platform. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE). 1--6. Google ScholarDigital Library
- Chen, G., Chen, H., Haurylau, M., Nelson, N. A., Albonesi, D. H., Fauchet, P. M., and Friedman, E. G. 2007. Predictions of CMOS compatible on-chip optical interconnect. VLSI J. Integration 40, 4, 434--446. Google ScholarDigital Library
- Chen, X., Mohamed, M., Schwartz, B., Li, Z., Shang, L., and Mickelson, A. 2010. Racetrack filters for nanophotonic on-chip networks. In Proceedings of the Conference on Integrated Photonics Research, Silicon and Nanophotonics (ITPR).Google Scholar
- Cho, H., Kapur, P., and Saraswat, K. 2004. Power comparison between high-speed electrical and optical interconnects for inter-chip communication. In Proceedings of the IEEE International Interconnect Technology Conference (IITC). 116--118.Google Scholar
- Cianchetti, M. J., Kerekes, J. C., and Albonesi, D. H. 2009. Phastlane: A rapid transit optical routing network. In Proceedings of the 36th Annual International Symposium Computer Architecture (ISCA). 441--450. Google ScholarDigital Library
- Dally, W. and Seitz, C. 1987. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. C-36 5, 547--553. Google ScholarDigital Library
- Dally, W. and Towles, B. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the Design Automation Conference (DAC). 684--689. Google ScholarDigital Library
- Das, R., Eachempati, S., Mishra, A., Narayanan, V., and Das, C. 2009. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. In Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA). 175--186.Google Scholar
- Dong, P., Preble, S. F., and Lipson, M. 2007. All-optical compact silicon comb switch. Opt. Express 15, 15, 9600--9605.Google ScholarCross Ref
- Doylend, J. and Knights, A. 2006. Design and simulation of an integrated fiber-to-chip coupler for silicon-on-insulator waveguides. IEEE J. Sel. Topics Quantum Electron. 12, 6, 1363--1370.Google ScholarCross Ref
- Gu, H., Xu, J., and Wang, Z. 2008. A novel optical mesh network-on-chip for gigascale systems-on-chip. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). 1728--1731.Google Scholar
- Gu, H., Mo, K. H., Xu, J., and Zhang, W. 2009. A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 19--24. Google ScholarDigital Library
- Hu, J. and Marculescu, R. 2003. Energy-aware mapping for tile-based NOC architectures under performance constraints. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP_DAC). 233--239. Google ScholarDigital Library
- Hu, J., Ogras, U. Y., and Marculescu, R. 2006. System-level buffer allocation for application-specific networks-on-chip router design. IEEE Trans. Computer-Aided Design Integr. Circuits Syst. 25, 12, 2919--2933. Google ScholarDigital Library
- Ji, C., Wang, J., Soderstrom, D., and Giovane, L. 2009. High data rate 850 nm oxide VCSEL for 20 Gb/s application and beyond. In Proceedings of the Communications and Photonics Conference and Exhibition, Asia (ACP). 1--2.Google Scholar
- Kash, J. 2007. Intrachip optical networks for a future supercomputer-on-a-chip. In Proceedings of Photonics in Switching (PS). 55--56.Google ScholarCross Ref
- Kirman, N., Kirman, M., Dokania, R., Martinez, J., Apsel, A., Watkins, M., and Albonesi, D. 2006. Leveraging optical technology in future bus-based chip multiprocessors. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 492--503. Google ScholarDigital Library
- Kirman, N. and Martínez, J. F. 2010. A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. In Proceedings of the 15th Annual International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 15--28. Google ScholarDigital Library
- Kromer, C., Sialm, G., Berger, C., Morf, T., Schmatz, M., Ellinger, F., Erni, D., Bona, G.-L., and Jackel, H. 2005. A 100-mW 4 x 10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects. IEEE J. Solid-State Circuits 40, 12, 2667--2679.Google ScholarCross Ref
- Kumar, S., Jantsch, A., Soininen, J.-P., Forsell, M., Millberg, M., Oberg, J., Tiensyrja, K., and Hemani, A. 2002. A network on chip architecture and design methodology. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 105--112. Google ScholarDigital Library
- Lee, H. G., Chang, N., Ogras, U. Y., and Marculescu, R. 2007. On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ACM Trans. Des. Autom. Electron. Syst. 12, 3, 1--20. Google ScholarDigital Library
- Lee, B., Biberman, A., Dong, P., Lipson, M., and Bergman, K. 2008. All-optical comb switch for multiwavelength message routing in silicon photonic networks. IEEE Photon. Technol. Lett. 20, 10, 767--769.Google ScholarCross Ref
- Liu, W., Yuan, M., He, X., Gu, Z., and Liu, X. 2008. Efficient SAT-Based mapping and scheduling of homogeneous synchronous dataflow graphs for throughput optimization. In Proceedings of the Real-Time Systems Symposium (RTSS). 92--504. Google ScholarDigital Library
- Lott, J. A., Ledentsov, N. N., Shchukin, V. A., Mutig, A., Blokhin, S. A., Nadtochiy, A. M., Fiol, G., and Bimberg, D. 2010. 850 nm VCSELs for up to 40 Gbit/s short reach data links. In Proceedings of the Conference on Lasers and Electro-Optics (CLEO) and Quantum Electronics and Laser Science Conference (QELS). 1--2.Google Scholar
- Majer, M., Bobda, C., Ahmadinia, A., and Teich, J. 2005. Packet routing in dynamically changing networks on chip. In Proceedings of the 19th IEEE International Symposium on Parallel and Distributed Processing (PDPTA). Google ScholarDigital Library
- Masini, G., Capellini, G., Witzens, J., and Gunn, C. 2007. A 1550nm, 10Gbps monolithic optical receiver in 130nm CMOS with integrated Ge waveguide photodetector. In Proceedings of the 4th IEEE International Conference Group IV Photonics (GFP). 1--3.Google Scholar
- Michelogiannakis, G., Pnevmatikatos, D., and Katevenis, M. 2007. Approaching ideal NOC latency with pre-configured routes. In Proceedings of the 1st International Symposium of Networks-on-Chip (NOCS). 153--162. Google ScholarDigital Library
- Morris, R. and Kodi, A. K. 2010. Exploring the design of 64- and 256-core power efficient nanophotonic interconnect. IEEE J. Sel. Topics Quantum Electron. PP, 99, 1--8.Google Scholar
- Ni, L. and McKinley, P. 1993. A survey of wormhole routing techniques in direct networks. Comput. 26, 2, 62--76. Google ScholarDigital Library
- O’Connor, I. 2004. Optical solutions for system-level interconnect. In Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP). 79--88. Google ScholarDigital Library
- O’Connor, I., Tissafi-Drissi, F., Navarro, D., Mieyeville, F., Gaffiot, F., Dambre, J., de Wilde, M., Stroobandt, D., and Briere, M. 2006. Integrated optical interconnect for on-chip data transport. In Proceedings of the IEEE North-East Workshop on Circuits and Systems (NEWCAS). 209--209.Google Scholar
- Pan, Y., Kim, J., and Memik, G. 2010. Flexishare: Channel sharing for an energy-efficient nanophotonic crossbar. In Proceedings of the IEEE 16th International Symposium on High Performance Computer Architecture (HPCA). 1--12.Google Scholar
- Pan, Y., Kumar, P., Kim, J., Memik, G., Zhang, Y., and Choudhary, A. 2009. Firefly: Illuminating future network-on-chip with nanophotonics. In Proceedings of the 36th International Symposium on Computer Architecture (ISCA). Google ScholarDigital Library
- Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 8, 1025--1040. Google ScholarDigital Library
- Pasricha, S. and Dutt, N. 2008. Trends in emerging on-chip interconnect technologies. Inform. Media Technol. 3, 4, 630--645.Google Scholar
- Perkins, J. and Fonstad, C. 2007. Low threshold VCSELs recess-integrated on Si-CMOS ICs. In Proceedings of the Conference on Lasers and Electro-Optics (CLEO). 1--2.Google Scholar
- Perkins, J. M., Simpkins, T. L., Warde, C., and Clifton G. Fonstad, J. 2008. Full recess integration of small diameter low threshold VCSELs within Si-CMOS ICs. Opt. Express 16, 18, 13955--13960.Google ScholarCross Ref
- Petracca, M., Lee, B., Bergman, K., and Carloni, L. 2008. Design exploration of optical interconnection networks for chip multiprocessors. In Proceedings of the 16th IEEE Symposium High Performance Interconnects (HOTI). 31--40. Google ScholarDigital Library
- Poon, A. W., Xu, F., and Luo, X. 2008. Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip. Silicon Photonics III 6898, 1.Google Scholar
- Poulton, J., Palmer, R., Fuller, A., Greer, T., Eyles, J., Dally, W., and Horowitz, M. 2007. A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS. IEEE J. Solid-State Circuits 42, 12, 2745--2757.Google ScholarCross Ref
- Rijpkema, E., Goossens, K., Radulescu, A., Dielissen, J., van Meerbergen, J., Wielage, P., and Waterlander, E. 2003. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE). Google ScholarDigital Library
- Shacham, A., Bergman, K., and Carloni, L. 2008. Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans. Comput. 57, 9, 1246--1260. Google ScholarDigital Library
- Syrbu, A., Mereuta, A., Iakovlev, V., Caliman, A., Royo, P., and Kapon, E. 2008. 10 Gbps VCSELs with high single mode output in 1310nm and 1550 nm wavelength bands. In Proceedings of the Conference on Optical Fiber Communication/National Fiber Optic Engineers (OFC/NFOEC). 1--3.Google Scholar
- Vantrease, D., Schreiber, R., Monchiero, M., McLaren, M., Jouppi, N., Fiorentino, M., Davis, A., Binkert, N., Beausoleil, R., and Ahn, J. 2008. Corona: System implications of emerging nanophotonic technology. In Proceedings of the 35th International Symposium on Computer Architecture (ISCA). 153--164. Google ScholarDigital Library
- Vlasov, Y., Green, W. M. J., and Xia, F. 2008. High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks. Nature Photonics 2, 242--246.Google ScholarCross Ref
- Xia, F. A., Sekaric, L. A., and Vlasov, Y. T. 2007. Ultracompact optical buffers on a silicon chip. Nature Photonics 1, 65--71.Google ScholarCross Ref
- Xiao, S., Khan, M. H., Shen, H., and Qi, M. 2007. Multiple-channel silicon micro-resonator based filters for WDM applications. Opt. Express 15, 12, 7489--7498.Google ScholarCross Ref
- Xu, J., Wolf, W., Henkel, J., and Chakradhar, S. 2005. 264 HDTV decoder using application-specific networks-on-chip. In Proceedings of the IEEE International Conference on Multimedia and Expo (ICME). 1508--1511.Google Scholar
- Yin, T., Cohen, R., Morse, M. M., Sarid, G., Chetrit, Y., Rubin, D., and Paniccia, M. J. 2007. 31 GHz Ge N-I-P waveguide photodetectors on silicon-on-insulator substrate. Opt. Express 15, 21, 13965--13971.Google ScholarCross Ref
- Young, I., Mohammed, E., Liao, J., Kern, A., Palermo, S., Block, B., Reshotko, M., and Chang, P. 2009. Optical I/O technology for tera-scale computing. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). 468--469.Google Scholar
- Zheng, X., Liu, F., Patil, D., Thacker, H., Luo, Y., Pinguet, T., Mekis, A., Yao, J., Li, G., Shi, J., Raj, K., Lexau, J., Alon, E., Ho, R., Cunningham, J. E., and Krishnamoorthy, A. V. 2010. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems. Opt. Express 18, 1, 204--211.Google ScholarCross Ref
Index Terms
- A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
Recommendations
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
ISVLSI '10: Proceedings of the 2010 IEEE Annual Symposium on VLSINetwork-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocessor system-on-chip (MPSoC). However, traditional NoCs using metallic interconnects consume significant amount of power to deliver even higher ...
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip
Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated ...
A thermal-sensitive design of a 3D torus-based optical NoC architecture
AbstractIn order to overcome limitations of traditional electronic interconnects in terms of power efficiency and bandwidth density, optical networks-on-chip (NoC) based on silicon photonics have been proposed as an emerging on-chip ...
Highlights- A thermal-sensitive design approach of a 3D torus-based optical NoC architecture is proposed.
Comments