- 1.C. Ahlberg and B. Shneiderman. The Alphaslider: A compact and rapid selector. In Proceedings of A CM Conference on Computer-Human Interaction, pages 365-371. ACM, April 1994. Google ScholarDigital Library
- 2.D. B. Diner. Sub-pixel resolution in 3-d television for teleoperation. In International Conference on Systems, Man, and Cybernetics, 1991.Google Scholar
- 3.P. M. Fitts and J. R. Peterson. Information capacity of discrete motor responses. Journal of Experimental Psychology, (67):103-112, 1964.Google Scholar
- 4.K. Kashiwagi, G. R. Borden IV, and T. Masui. "FineSlider": a high precision slider (in Japanese). In Tenth Human Interface Symposium of SICE, pages 297-300, October 1994.Google Scholar
- 5.T. Masui, K. Kashiwagi, and G. R. Borden IV. Elastic graphical interfaces for precise data manipulation. In CHI'95 Conference Companion, pages 143- 144. ACM, 1995. Google ScholarDigital Library
- 6.M. Osada, H.Liao, and B. Shneiderman. Alphaslider: Seaching textual lists with sliders. In Proceedings of Ninth Annual Japanese Conference on Human Interface, October 1993.Google Scholar
- 7.J. Rekimoto, Y. Ayatsuka, H. Uoi, and T. Arai. Adding another communication channel to reality: An experience with a chat-augmented conference. In CHI'93 Summary (la~e breaking results), pages pp.271-272. ACM, April 1998. Google ScholarDigital Library
Index Terms
- Popup vernier: a tool for sub-pixel-pitch dragging with smooth mode transition
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