Qutaiba Alasad
Pramod Subramanyan
Skip Abstract Section
Abstract
Untrusted foundries pose threats of integrated circuit (IC) piracy and counterfeiting, and this has motivated research into logic locking. Strong logic locking approaches potentially prevent piracy and counterfeiting by preventing unauthorized replication and use of ICs. Unfortunately, recent work has shown that most state-of-the-art logic locking techniques are vulnerable to attacks that utilize Boolean Satisfiability (SAT) solvers.
In this article, we extend our prior work on using silicon nanowire (SiNW) field-effect transistors (FETs) to produce obfuscated ICs that are resistant to reverse engineering attacks, such as the sensitization attack, SAT and approximate SAT attacks, as well as tracked signal attacks. Our method is based on exchanging some logic gates in the original design with a set of polymorphic gates (PLGs), designed using SiNW FETs, and augmenting the circuit with a small block, whose output is untraceable, namely, URSAT. The URSAT may not offer very strong resilience against the combined AppSAT-removal attack. Strong URSAT is achieved using only CMOS-logic gates, namely, S-URSAT. The proposed technique, S-URSAT + PLG-based traditional encryption, designed using SiNW FETs, increases the security level of the design to robustly thwart all existing attacks, including combined AppSAT-removal attack, with small penalties. Then, we evaluate the effectiveness of our proposed methods and subject it to a thorough security analysis. We also evaluate the performance penalty of the technique and find that it results in very small overheads in comparison to other works. The average area, power, and delay overheads of implementing 64 baseline key-bits of S-URSAT for small benchmarks are 5.03%, 2.60%, and −2.26%, respectively, while for large benchmarks they are 2.37%, 1.18%, and −1.93%.
- P. Subramanyan, N. Tsiskaridze, W. Li, A. Gascón, W. Tan, A. Tiwari, N. Shankar, S. Seshia, and S. Malik. 2014. Reverse engineering digital circuits using structural and functional analyses. IEEE Trans. Emerg. Topics Comput. 2, 1 (2014).Google Scholar
Cross Ref
- Ujjwal Guin, Qihang Shi, Domenic Forte, and Mark M. Tehranipoor. 2016. FORTIS: A comprehensive solution for establishing forward trust for protecting IPs and ICs. ACM Trans. Des. Autom. Electron. Syst. 21, 4 (2016).Google ScholarDigital Library
- B. Shakya, N. Asadizanjani, D. Forte, and M. Tehranipoor. 2016. Chip editor: Leveraging circuit edit for logic obfuscation and trusted fabrication. In Proceedings of the IEEE International Conference on Computer-Aided Design.Google Scholar
- SEMI. 2008. Innovation is at risk as semiconductor equipment and materials industry loses up to $ 4 billion annually due to IP infringement. www.semi.org/en.Google Scholar
- Global Intelligent Property Center U.S. Chamber of Commerce (GIPC). 2016. Measuring the magnitude of global counterfeiting. U.S. Chamber of Commerce. https://www.uschamber.com/sites/default/files/documents/files/measuringthemagnitudeofglobalcounterfeiting.pdf.Google Scholar
- Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. Logic encryption: A fault analysis perspective. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’12).Google Scholar
- Amin Rezaei, Yuanqi Shen, and Hai Zhou. 2019. Rescuing logic encryption in post-SAT era by locking and obfuscation. In Cryptology ePrint Archive, Report 2019/1463. Retrieved from https://eprint.iacr.org/2019/1463.Google Scholar
- J. A. Roy, F. Koushanfar, and I. L. Markov. 2008. EPIC: Ending piracy of integrated circuits. In Proceedings of the Design, Automation and Test in Europe Conference.Google Scholar
- J. A. Roy and F. Koushanfar and I. L. Markov. 2010. Ending piracy of integrated circuits. Computer 43, 10 (2010).Google ScholarDigital Library
- J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri. 2015. Fault analysis-based logic encryption. IEEE Trans. Comput. 64, 2 (2015).Google ScholarCross Ref
- Qutaiba Alasad et al. 2017. E2LEMI: Energy-efficient logic encryption using multiplexer insertion. Electronics 6 (2017).Google Scholar
- Q. Alasad, J. Yuan, and Y. Bi. 2017. Logic locking using hybrid CMOS and emerging SiNW FETs. Electronics 6 (2017).Google Scholar
- J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. 2012. Security analysis of logic obfuscation. In Proceedings of the Design Automation Conference.Google Scholar
- P. Subramanyan, S. Ray, and S. Malik. 2015. Evaluating the security of logic encryption algorithms. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST’15).Google Scholar
- Yang Xie and Ankur Srivastava. 2016. Mitigating SAT attack on logic locking. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems.Google ScholarCross Ref
- M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. 2018. Removal attacks on logic locking and camouflaging techniques. IEEE Trans. Emerg. Topics Comput. 1, 1 (2018).Google Scholar
- K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin. 2017. AppSAT: Approximately deobfuscating integrated circuits. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST’17).Google Scholar
- Y. Xie and A. Srivastava. 2018. Anti-SAT: Mitigating SAT attack on logic locking. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 38, 2 (2018).Google Scholar
- M. Yasin, B. Mazumdar, J. J. V. Rajendran, and O. Sinanoglu. 2016. SARLock: SAT attack resistant logic locking. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST’16).Google Scholar
- Muhammad Yasinet al.2017. What to lock?: Functional and parametric locking. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’17).Google Scholar
- M. Nabeel M. Ashraf J. Rajendran M. Yasin, A. Sengupta and O. Sinanoglu. 2017. Provably-secure logic locking: From theory to practice. In Proceedings of the ACM Conference on Computer and Communications Security (CCS’17).Google Scholar
- Q. Alasad and J. Yuan. 2017. Logic obfuscation against IC reverse engineering attacks using PLGs. In Proceedings of the IEEE International Conference on Computer Design.Google Scholar
- J. Appenzeller, J. Knoch, E. Tutuc, M. Reuter, and S. Guha. 2006. Dual-gate silicon nanowire transistors with nickel silicide contacts. In Proceedings of the International Electron Devices Meeting (IEDM’06). 1--4.Google Scholar
- M. D. Marchi, J. Zhang, S. Frache, D. Sacchetto, P. Gaillardon, Y. Leblebici, and G. D. Micheli. 2014. Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs. IEEE Electron Dev. Lett. 35, 8 (2014).Google ScholarCross Ref
- M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P. E. Gaillardon, Y. Leblebici, and G. De Micheli. 2012. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs. In Proceedings of the International Electron Devices Meeting.Google Scholar
- Qutaiba Alasad, Jiann Yuan, and Deliang Fan. 2017. Leveraging all-spin logic to improve hardware security. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’17).Google ScholarDigital Library
- H. Zhou. 2017. A humble theory and application for logic encryption. Cryptol. ePrint Arch. 2017, 1 (2017).Google Scholar
- Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, and David Z. Pan. 2016. Provably secure camouflaging strategy for IC protection. In Proceedings of the 35th International Conference on Control, Automation and Diagnosis.Google Scholar
- Yuanqi Shen and Hai Zhou. 2017. Double DIP: Re-evaluating security of logic encryption algorithms. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’17).Google ScholarDigital Library
- Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, and Domenic Forte. 2017. Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems.Google ScholarCross Ref
- D. Sirone and P. Subramanyan. 2019. Functional analysis attacks on logic locking. In Design, Automation and Test in Europe Conference (DATE’19). 936--939. DOI:http://dx.doi.org/10.23919/DATE.2019.8715163Google Scholar
- D. Sirone and P. Subramanyan. 2018. Functional analysis attacks on logic locking. arXiv preprint arXiv:1811.12088.Google Scholar
- A. Sengupta et al. 2018. ATPG-based cost-effective, secure logic locking. In Proceedings of the IEEE 36th VLSI Test Symposium (VTS’18).Google ScholarCross Ref
- Abhrajit Sengupta, Mohammed Nabeel, Mohammed Ashraf, and Ozgur Sinanoglu. 2018. Customized locking of IP blocks on a multi-million-gate SoC. In Proceedings of the International Conference on Computer-Aided Design.Google ScholarDigital Library
- Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, and Yier Jin. 2017. Cyclic obfuscation for creating SAT-unresolvable circuits. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’17).Google ScholarDigital Library
- Hai Zhou, Ruifeng Jiang, and Shuyu Kong. 2017. CycSAT: SAT-based attack on cyclic logic encryptions. In Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD’17).Google ScholarCross Ref
- Y. Xie and A. Srivastava. 2017. Delay locking: Security enhancement of logic locking against IC counterfeiting and overproduction. In Proceedings of the 54th ACM/EDAC/IEEE Design Automation Conference (DAC’17).Google Scholar
- A. Chakraborty, Y. Liu, and A. Srivastava. 2018. TimingSAT: Timing profile embedded SAT attack. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1--6. DOI:http://dx.doi.org/10.1145/3240765.3240857.Google Scholar
- Kimia Zamiri Azar et al. 2019. SMT attack: Next generation attack on obfuscated circuits with capabilities and performance beyond the SAT attacks. IACR Trans. Crypto. Hardw. Embed. Syst. 2019, 1 (2019).Google Scholar
- Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, and Avesta Sasan. 2019. Threats on logic locking: A decade later. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’19).Google Scholar
- Pim Tuyls, Geert-Jan Schrijen, Boris Škorić, Jan van Geloven, Nynke Verhaegh, and Rob Wolters. 2006. Read-proof hardware from protective coatings. In Proceedings of the 8th International Conference on Cryptographic Hardware and Embedded Systems (CHES'06), vol 4249. Springer-Verlag, Berlin.Google ScholarDigital Library
- G. K. Contreras, M. T. Rahman, and M. Tehranipoor. 2013. Secure split-test for preventing IC piracy by untrusted foundry and assembly. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.Google Scholar
- H. Wang, D. Forte, M. M. Tehranipoor, and Q. Shi. 2017. Probing attacks on integrated circuits: Challenges and research opportunities. IEEE Des. Test 34, 5 (Oct. 2017), 63--71. DOI:http://dx.doi.org/10.1109/MDAT.2017.2729398Google ScholarCross Ref
- H. Wang, Qihang Shi Shi, Adib Nahiyan, D. Forte, and Mark M. Tehranipoor. 2019. A physical design flow against front-side probing attacks by internal shielding. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 2019, 1 (2019).Google Scholar
- H. Wang, Q. Shi, D. Forte, and M. M. Tehranipoor. 2019. Probing assessment framework and evaluation of antiprobing solutions. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27, 6 (2019).Google ScholarDigital Library
- S. Skorobogatov and Ch. Woods. 2012. In the blink of an eye: There goes your AES key. IACR Crypto. ePrint 2012, 1 (2012).Google Scholar
- F. Courbon, S. Skorobogatov, and Ch. Woods. 2016. Direct charge measurement in floating gate transistors of flash EEPROM using scanning electron microscopy. In Proceedings of the 32nd Information Science, Technology and Applications Conference.Google Scholar
- Swarup Bhunia and Mark Tehranipoo. 2019. Physical attacks and countermeasures. In Hardware Security: A Hands-on Learning Approach. Elsevier Inc., 246--282.Google Scholar
- J. Alasad, Q. Taheri, S. Yuan, and J.-S. Lin. 2017. Ultra-low-power design and hardware security using emerging technologies for Internet of Things. Electronics 6 (2017).Google Scholar
- A. Stoica et al. 2004. Taking evolutionary circuit design from experimentation to implementation: Some useful techniques and a silicon demonstration. In Proceedings of the IEEE Computers and Digital Techniques Conference.Google ScholarCross Ref
- Adrian Stoica, Ricardo S. Zebulum, and Didier Keymeulen. 2001. Polymorphic electronics. In Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware (ICES’01).Google ScholarDigital Library
- R. Ruzicka. 2007. New polymorphic NAND/XOR gate. In Proceedings of 7th WSEAS International Conference on Applied Computer Science. Citeseer.Google Scholar
- K. Huang and R. Zhao. 2016. Magnetic domain-wall racetrack memory-based nonvolatile logic for low-power computing and fast run-time-reconfiguration. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24, 9 (2016).Google ScholarCross Ref
- F. Parveen, Z. He, S. Angizi, and D. Fan. 2017. Hybrid polymorphic logic gate with 5-terminal magnetic domain wall motion device. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’17).Google Scholar
- Y. Zhang, B. Yan, W. Wu, H. Li, and Y. Chen. 2015. Giant spin hall effect (GSHE) logic design for low power application. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’15). 1000--1005.Google Scholar
- S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, and S. Rakheja. 2018. Advancing hardware security using polymorphic and stochastic spin-hall effect devices. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’18).Google Scholar
- Arman Roohi, Ramtin Zand, and Ronald F. DeMara. 2018. Logic-encrypted synthesis for energy-harvesting-powered spintronic-embedded datapath design. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’18).Google Scholar
- T. Winograd, H. Salmani, H. Mahmoodi, K. Gaj, and H. Homayoun. 2016. Hybrid STT-CMOS designs for reverse-engineering prevention. In Proceedings of the 53rd ACM/EDAC/IEEE Design Automation Conference (DAC’16).Google Scholar
- J. Yang, X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. 2019. Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 38, 1 (2019).Google ScholarDigital Library
- S. Angizi, H. Jiang, R. F. DeMara, J. Han, and D. Fan. 2018. Majority-based spin-CMOS primitives for approximate computing. IEEE Trans. Nanotech. 17, 4 (2018).Google Scholar
- D. Nikonov, C. Lin, S. Manipatruni et al. 2019. Scalable energy-efficient magnetoelectric spin--orbit logic. Nature 565, 3 (2019).Google Scholar
- S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, and S. Rakheja. 2019. Spin-orbit torque devices for hardware security: From deterministic to probabilistic regime. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 2019, 1 (2019).Google Scholar
- M. Marchi, D. Sacchetto, J. Zhang, S. Frache, P. Gaillardon, Y. Leblebici, and G. Micheli. 2014. Top-down fabrication of gate-all-around vertically stacked silicon nanowire FETs with controllable polarity. IEEE Trans. Nanotech. 13, 6 (2014).Google ScholarCross Ref
- F. Brglez and H. Fujiwara. 1985. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’85). IEEE Press, Piscataway, N.J.Google Scholar
- F. Brglez, D. Bryan, and K. Kozminski. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 3. 1929--1934. DOI:http://dx.doi.org/10.1109/ISCAS.1989.100747Google Scholar
- F. Corno, M. S. Reorda, and G. Squillero. 2000. RT-level ITC'99 benchmarks and first ATPG results. IEEE Design and Test of Computers 17, 3 (2000).Google Scholar
- Robert Brayton and Alan Mishchenko. 2010. ABC: An academic industrial-strength verification tool. In Computer Aided Verification, Tayssir Touili, Byron Cook, and Paul Jackson (Eds.), Vol. 6174. Springer, Berlin, Heidelberg.Google Scholar
- P. Gaillardon, L. Amaru, J. Zhang, and G. De Micheli. 2014. Advanced system on a chip design based on controllable-polarity FETs. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’14).Google Scholar
- Qutaiba Alasad et al. 2018. Resilient AES against side-channel attack using all-spin logic. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’18).Google Scholar
- Paul Kocher, Joshua Jaffe, and Benjamin Jun. 1999. Differential power analysis. In Advances in Cryptology, Michael Wiener (Ed.). Springer Berlin, 388--397.Google Scholar
- Joshua Jaffe Paul Kocher and Benjamin Jun. 1998. Introduction to differential power analysis and related attacks. Retrieved from http://www.cryptography.com/dpa/technical.Google Scholar
- Shahin Tajik et al. 2017. On the power of optical contactless probing: Attacking bitstream encryption of FPGAs. In Proceedings of the ACM SIGSAC Conference on Computer and Communications Security.Google Scholar
- Y. Bi, K. Shamsi, J. Yuan, F. Standaert, and Y. Jin. 2016. Leverage emerging technologies for DPA-resilient block cipher design. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’16). 1538--1543.Google Scholar
- M. N. I. Khan, S. Bhasin, A. Yuan, A. Chattopadhyay, and S. Ghosh. 2017. Side-channel attack on STTRAM based cache for cryptographic application. In Proceedings of the IEEE International Conference on Computer Design (ICCD’17).Google Scholar
Index Terms
- Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks
Recommendations
Resilient and Secure Hardware Devices Using ASL
Hardware and Algorithms for Efficient Machine LearningDue to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, Third-Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and ...
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview
The globalization of the semiconductor supply chain introduces ever-increasing security and privacy risks. Two major concerns are IP theft through reverse engineering and malicious modification of the design. The latter concern in part relies on ...
Reduced Overhead Gate Level Logic Encryption
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSIUntrusted third-parties are found throughout the integrated circuit (IC) design flow resulting in potential threats in IC reliability and security. Threats include IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion ...
Comments