Qutaiba Alasad
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Abstract
Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, Third-Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. To thwart such attacks, ICs can be protected using logic encryption techniques. However, strong resilient techniques incur significant overheads. Side-channel attacks (SCAs) further complicate matters by introducing potential attacks post fabrication. One of the most severe SCAs is power analysis (PA) attacks, in which an attacker can observe the power variations of the device and analyze them to extract the secret key. PA attacks can be mitigated via adding large extra hardware; however, the overheads of such solutions can render them impractical, especially when there are power and area constraints.
All Spin Logic Device (ASLD) is one of the most promising spintronic devices due to its unique properties: small area, no spin-charge signal conversion, zero leakage current, non-volatile memory, high density, low operating voltage, and its compatibility with conventional CMOS technology. In this article, we extend the work in Reference [1] on the usage of ASLD to produce secure and resilient circuits that withstand IC attacks (during the fabrication) and PA attacks (after fabrication), including reverse engineering attacks. First, we show that ASLD has another unique feature: identical power dissipation through the switching operations, where such properties can be effectively used to prevent PA and IC attacks. We then evaluate the proposed ASLD-based on performance overheads and security guarantees.
- Qutaiba Alasad, Jiann Yuan, and Jie Lin. 2018. Resilient AES against side-channel attack using all-spin logic. In Proceedings of the 2018 on Great Lakes Symposium on VLSI (GLSVLSI’18).Google Scholar
Digital Library
- Ujjwal Guin, Qihang Shi, Domenic Forte, and Mark M. Tehranipoor. 2016. FORTIS: A comprehensive solution for establishing forward trust for protecting IPs and ICs. ACM Trans. Des. Autom. Electron. Syst. 21, 4 (May 2016).Google ScholarDigital Library
- Age Yeh. 2012. Trends in the Global IC Design Service Market. Retrieved from http://www.digitimes.com/news/a20120313RS400.html?chid=2/.Google Scholar
- Kaveh Shamsi, Meng Li, Kenneth Plaks, Saverio Fazzari, David Z. Pan, and Yier Jin. 2019. IP protection and supply chain security through logic obfuscation: A systematic overview. ACM Trans. Des. Autom. Electron. Syst. 24, 6 (September 2019).Google ScholarDigital Library
- R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor. 2010. Trustworthy hardware: Identifying and classifying hardware trojans. Computer 43, 10 (October 2010), 39--46. DOI:http://dx.doi.org/10.1109/MC.2010.299Google ScholarDigital Library
- J. Roy, F. Koushanfar, and I. L. Markov. 2008. EPIC: Ending piracy of integrated circuits. In Proceedings of the 2008 Design, Automation and Test in Europe. 1069--1074. DOI:http://dx.doi.org/10.1109/DATE.2008.4484823Google Scholar
- J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri. 2015. Fault analysis-based logic encryption. IEEE Trans. Comput. 64, 2 (February 2015), 410--424. DOI:http://dx.doi.org/10.1109/TC.2013.193Google ScholarDigital Library
- Qutaiba Alasad, Jiann-Shuin Yuan, and Yu Bi. 2017. Logic locking using hybrid CMOS and emerging SiNW FETs. Electronics 6 (2017). DOI:http://dx.doi.org/10.3390/electronics6030069Google Scholar
- Qutaiba Alasad, Yu Bi, and Jiann-Shuin Yuan. 2017. E2LEMI: Energy-efficient logic encryption using multiplexer insertion. Electronics 6, 1 (2017). DOI:http://dx.doi.org/10.3390/electronics6010016Google Scholar
- Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2012. Security analysis of logic obfuscation. In Proceedings of the 49th Annual Design Automation Conference (DAC’12). 83--89.Google ScholarDigital Library
- P. Subramanyan, S. Ray, and S. Malik. 2015. Evaluating the security of logic encryption algorithms. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST’15). DOI:http://dx.doi.org/10.1109/HST.2015.7140252Google ScholarCross Ref
- M. Yasin, B. Mazumdar, J. J. V. Rajendran, and O. Sinanoglu. 2016. SARLock: SAT attack resistant logic locking. In Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST’16).Google Scholar
- Yang Xie and Ankur Srivastava. 2016. Mitigating Attack on Logic Locking. Springer, Berlin.Google Scholar
- M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. 2018. Removal attacks on logic locking and camouflaging techniques. IEEE Trans. Emerg. Top. Comput. (2018). DOI:http://dx.doi.org/10.1109/TETC.2017.2740364Google Scholar
- Yuanqi Shen and Hai Zhou. 2017. Double DIP: Re-evaluating security of logic encryption algorithms. In Proceedings of the on Great Lakes Symposium on VLSI 2017 (GLSVLSI’17). 179--184.Google ScholarDigital Library
- K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin. 2017. AppSAT: Approximately deobfuscating integrated circuits. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST’17).Google Scholar
- Muhammad Yasin et al. 2017. Provably-secure logic locking: From theory to practice. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (CCS’17).Google Scholar
- K. Shamsi, T. Meade, M. Li, D. Z. Pan, and Y. Jin. 2019. On the approximation resiliency of logic locking and IC camouflaging schemes. IEEE Trans. Inf. Forens. Secur. (2019).Google Scholar
- Pim Tuyls et al. 2006. Read-proof hardware from protective coatings. In Proceedings of the Cryptographic Hardware and Embedded Systems (CHES’06). Springer, Berlin.Google Scholar
- Paul Kocher, Joshua Jaffe, and Benjamin Jun. 1999. Differential power analysis. In Proceedings of the Annual Conference on Advances in Cryptology (CRYPTO’99), Michael Wiener (Ed.). Springer, Berlin, 388--397.Google ScholarCross Ref
- P. Kocher. 2005. Design and validation strategies for obtaining assurance in countermeasures to power analysis and related. In NIST Physical Security.Google Scholar
- S. Skorobogatov and Ch. Woods. 2012. In the blink of an eye: There goes your AES key. In IACR Crypt. ePrint Arch., no. 296 (2012).Google Scholar
- X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, A. Raghunathan, and K. Roy. 2016. Spin-transfer torque devices for logic and memory: Prospects and perspectives. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. (2016).Google Scholar
- A. Jaiswal et al. 2017. Energy-efficient memory using magneto-electric switching of ferromagnets. IEEE Magn. Lett. 8 (2017). DOI:http://dx.doi.org/10.1109/LMAG.2017.2712685Google Scholar
- Y. Wang, L. Ni, C. H. Chang, and H. Yu. 2016. DW-AES: A domain-wall nanowire-based AES for high throughput and energy-efficient data encryption in non-volatile memory. IEEE Trans. Inf. Forens. Secur. (2016).Google Scholar
- M. N. I. Khan, S. Bhasin, A. Yuan, A. Chattopadhyay, and S. Ghosh. 2017. Side-channel attack on STTRAM based cache for cryptographic application. In Proceedings of the 2017 IEEE International Conference on Computer Design (ICCD’17). 33--40. DOI:http://dx.doi.org/10.1109/ICCD.2017.14Google ScholarCross Ref
- Qutaiba Alasad, Pramod Subramanyan, and Jiann-Shuin Yuan. Strong logic obfuscation with low overhead against IC reverse engineering attacks. ACM Trans. Des. Autom. Electron. Syst. DOI:http://dx.doi.org/10.1145/3398012Google Scholar
- Qutaiba Alasad, Jiann Yuan, and Deliang Fan. 2017. Leveraging all-spin logic to improve hardware security. In Proceedings of the on Great Lakes Symposium on VLSI 2017 (GLSVLSI’17).Google ScholarDigital Library
- M. Rostami, F. Koushanfar, and R. Karri. 2014. A primer on hardware security: Models, methods, and metrics. Proc. IEEE 102, 8 (August 2014), 1283--1295. DOI:http://dx.doi.org/10.1109/JPROC.2014.2335155Google ScholarCross Ref
- J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. 2012. Logic encryption: A fault analysis perspective. In Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 953--958.Google Scholar
- M. Yasin, J. J. Rajendran, O. Sinanoglu, and R. Karri. 2016. On improving the security of logic locking. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 35, 9 (September 2016), 1411--1424. DOI:http://dx.doi.org/10.1109/TCAD.2015.2511144Google ScholarDigital Library
- M. Li et al. 2018. Provably secure camouflaging strategy for IC protection. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. (2018).Google Scholar
- Muhammad Yasin et al. 2017. What to lock?: Functional and parametric locking. In Proceedings of the on Great Lakes Symposium on VLSI 2017 (GLSVLSI’17).Google Scholar
- Q. Alasad and J. Yuan. 2017. Logic obfuscation against IC reverse engineering attacks using PLGs. In Proceedings of the 2017 IEEE International Conference on Computer Design (ICCD’17). 341--344. DOI:http://dx.doi.org/10.1109/ICCD.2017.59Google ScholarCross Ref
- Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, and Domenic J. Forte. 2017. Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks. In IACR Cryptology ePrint Archive.Google Scholar
- K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin. 2017. AppSAT: Approximately deobfuscating integrated circuits. In Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST’17). 95--100. DOI:http://dx.doi.org/10.1109/HST.2017.7951805Google ScholarCross Ref
- Deepak Sirone and Pramod Subramanyan. 2018. Functional analysis attacks on logic locking. arxiv:1811.12088. Retrieved from http://arxiv.org/abs/1811.12088.Google Scholar
- A. Sengupta et al. 2018. ATPG-based cost-effective, secure logic locking. In Proceedings of the 2018 IEEE 36th VLSI Test Symposium (VTS’18).Google Scholar
- Abhrajit Sengupta, Mohammed Nabeel, Mohammed Ashraf, and Ozgur Sinanoglu. 2018. Customized locking of IP blocks on a multi-million-gate SoC. In Proceedings of the International Conference on Computer-Aided Design.Google ScholarDigital Library
- Kenneth Smith. 2009. Methodologies for Power Analysis Attacks on Hardware Implementations of AES. Thesis. Rochester Institute of Technology.Google Scholar
- R. Karri, K. Wu, P. Mishra, and Yongkook Kim. 2001. Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture. In Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 427--435. DOI:http://dx.doi.org/10.1109/DFTVS.2001.966796Google ScholarCross Ref
- F. Zhang and Z. J. Shi. 2011. Differential and correlation power analysis attacks on HMAC-whirlpool. In Proceedings of the 2011 8th International Conference on Information Technology—New Generations (ITNG’11).Google Scholar
- K. Tiri, M. Akmal, and I. Verbauwhede. 2002. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In Proceedings of the 28th European Solid-State Circuits Conference (ESSCIRC’02).Google Scholar
- Amir Moradi et al. 2011. Pushing the Limits: A Very Compact and a Threshold Implementation of AES. Springer, Berlin.Google Scholar
- P. Liu et al. 2010. A low overhead DPA countermeasure circuit based on ring oscillators. IEEE Trans. Circ. Syst. II (2010).Google Scholar
- X. Li et al. 2017. Energy-efficient side-channel attack countermeasure with awareness and hybrid configuration based on it. IEEE Trans. VLSI Syst. (2017).Google Scholar
- M. W. Allam and M. I. Elmasry. 2001. Dynamic current mode logic (DyCML): A new low-power high-performance logic style. IEEE J. Solid-State Circ. 36, 3 (March 2001), 550--558. DOI:http://dx.doi.org/10.1109/4.910495Google ScholarCross Ref
- Dongrong Zhang, Miao He, Xiaoxiao Wang, and M. Tehranipoor. 2017. Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain. In Proceedings of the 2017 IEEE 35th VLSI Test Symposium (VTS’17). 1--6.Google Scholar
- X. Wang, D. Zhang, M. He, D. Su, and M. Tehranipoor. 2018. Secure scan and test using obfuscation throughout supply chain. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 37, 9 (2018), 1867--1880.Google ScholarDigital Library
- D. Hisamoto et al. 2000. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electr. Devices 47, 12 (December 2000), 2320--2325. DOI:http://dx.doi.org/10.1109/16.887014Google Scholar
- P. Zhao, R. M. Feenstra, G. Gu, and D. Jena. 2013. SymFET: A proposed symmetric graphene tunneling field-effect transistor. IEEE Trans. Electr. Devices 60, 3 (March 2013), 951--957. DOI:http://dx.doi.org/10.1109/TED.2013.2238238Google ScholarCross Ref
- K. Roy, M. Sharad, D. Fan, and K. Yogendra. 2014. Computing with spin-transfer-torque devices: Prospects and perspectives. In Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI. 398--402. DOI:http://dx.doi.org/10.1109/ISVLSI.2014.120Google ScholarDigital Library
- H. Dery, P. Dalal, L. Cywinski, and L. J. Sham. 2007. Spin-based logic in semiconductors for reconfigurable large-scale circuits. Nature (2007).Google Scholar
- B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta. 2010. Proposal for an all-spin logic device with built-in memory. Nature 5 (2010).Google Scholar
- C. Augustine et al. 2011. Low-power functionality enhanced computation architecture using spin-based devices. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures.Google Scholar
- G. K. Contreras, M. T. Rahman, and M. Tehranipoor. 2013. Secure split-test for preventing IC piracy by untrusted foundry and assembly. In Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS’13).Google Scholar
- Kerem Yunus Camsari, Samiran Ganguly, and Supriyo Datta. 2015. Modular approach to spintronics. In 2015 Scientific Reports, Vol. 5.Google ScholarCross Ref
- Z. Pajouhi et al. 2015. Exploring spin-transfer-torque devices for logic applications. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. (2015).Google Scholar
- M. El Massad, S. Garg, and M. Tripunitara. 2019. The SAT attack on IC camouflaging: Impact and potential countermeasures. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. (2019), 1--1. DOI:http://dx.doi.org/10.1109/TCAD.2019.2926478Google Scholar
- M. Sharad, K. Yogendra, Kon-Woo Kwon, and K. Roy. 2013. Design of ultra high density and low power computational blocks using nano-magnets. In Proceedings of the International Symposium on Quality Electronic Design (ISQED’13).Google Scholar
- J. M. Renders et al. 1994. Hybridizing genetic algorithms with hill-climbing methods for global optimization: Two possible ways. In Proceedings of the IEEE Proceedings on EC.Google Scholar
- K. Martin and A. Sedra. 1981. Switched-capacitor building blocks for adaptive systems. IEEE Trans. Circ. Syst. 28, 6 (June 1981), 576--584. DOI:http://dx.doi.org/10.1109/TCS.1981.1085017Google ScholarCross Ref
- Stafford E. Tavares and Howard M. Heys. 1995. Avalanche characteristics of substitution-permutation encryption networks. IEEE Trans. Comput. (1995).Google Scholar
- The ISCAS-85 Benchmark Circuits. Retrieved from http://www.pld.ttu.ee/ maksim/benchmarks/iscas85/.Google Scholar
- F. Brglez, D. Bryan, and K. Kozminski. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems 1989, Vol. 3. 1929--1934. DOI:http://dx.doi.org/10.1109/ISCAS.1989.100747Google Scholar
- F. Corno, M. S. Reorda, and G. Squillero. 2000. RT-level ITC’99 benchmarks and first ATPG results. IEEE Des. Test Comput. 17, 3 (July 2000), 44--53. DOI:http://dx.doi.org/10.1109/54.867894Google ScholarDigital Library
- Meghna G. Mankalale and Sachin S. Sapatnekar. 2016. Optimized standard cells for all-spin logic. J. Emerg. Technol. Comput. Syst. (2016).Google Scholar
- Q. Tian and S. A. Huss. 2012. Power amount analysis: Another way to understand power traces in side channel attacks. In Proceedings of the 2nd International Conference on Digital Information Processing and Communications (ICDIPC’12).Google Scholar
- D. Sirone and P. Subramanyan. 2019. Functional analysis attacks on logic locking. In Proceedings of the 2019 Design, Automation Test in Europe Conference Exhibition (DATE’19). 936--939. DOI:http://dx.doi.org/10.23919/DATE.2019.8715163Google ScholarCross Ref
- Tobias Schneider and Amir Moradi. 2015. Leakage assessment methodology. In Proceedings of the Cryptographic Hardware and Embedded Systems (CHES’15), Tim Güneysu and Helena Handschuh (Eds.). Springer, Berlin, 495--513.Google ScholarDigital Library
- Tobias Schneider and Amir Moradi. 2015. Leakage Assessment Methodology—A Clear Roadmap for Side-Channel Evaluations. Cryptology ePrint Archive, Report 2015/207. Retrieved from https://eprint.iacr.org/2015/207.Google Scholar
- S. Mathew et al. 2014. 340mV--1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. In Proceedings of the Symposium on VLSI Circuits Digest of Technical Papers.Google Scholar
- Z. Abid et al. 2009. Efficient CMOL gate designs for cryptography applications. IEEE Trans. Nanotechnol. (2009).Google Scholar
- K. Huang and R. Zhao. 2016. Magnetic domain-wall racetrack memory-based nonvolatile logic for low-power computing and fast run-time-reconfiguration. IEEE Trans. VLSI Syst. 24, 9 (2016), 2861--2872.Google ScholarDigital Library
- F. Parveen, Z. He, S. Angizi, and D. Fan. 2017. Hybrid polymorphic logic gate with 5-terminal magnetic domain wall motion device. In Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’17). 152--157. DOI:http://dx.doi.org/10.1109/ISVLSI.2017.35Google ScholarCross Ref
- Y. Zhang, B. Yan, W. Wu, H. Li, and Y. Chen. 2015. Giant spin hall effect (GSHE) logic design for low power application. In Proceedings of the 2015 Design, Automation Test in Europe Conference Exhibition (DATE’15). 1000--1005.Google Scholar
- S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, and S. Rakheja. 2018. Advancing hardware security using polymorphic and stochastic spin-hall effect devices. In Proceedings of the 2018 Design, Automation Test in Europe Conference Exhibition (DATE’77).Google Scholar
- S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, and S. Rakheja. 2019. Spin-orbit torque devices for hardware security: From deterministic to probabilistic regime. IEEE Trans. Comput.-Aid. Design Integr. Circ. Syst. (2019).Google Scholar
- Arman Roohi, Ramtin Zand, and Ronald F. DeMara. 2018. Logic-encrypted synthesis for energy-harvesting-powered spintronic-embedded datapath design. In Proceedings of the 2018 on Great Lakes Symposium on VLSI (GLSVLSI’18).Google Scholar
- S. Angizi, H. Jiang, R. F. DeMara, J. Han, and D. Fan. 2018. Majority-based spin-CMOS primitives for approximate computing. IEEE Trans. Nanotechnol. 17, 4 (July 2018), 795--806. DOI:http://dx.doi.org/10.1109/TNANO.2018.2836918Google Scholar
- S. Angizi, Z. He, A. Awad, and D. Fan. 2019. MRIMA: An MRAM-based in-memory accelerator. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. (2019), 1--1. DOI:http://dx.doi.org/10.1109/TCAD.2019.2907886Google Scholar
- F. Courbon, S. Skorobogatov, and Ch. Woods. 2016. Direct charge measurement in floating gate transistors of flash EEPROM using scanning electron microscopy. In Proceedings of the 32nd International Symposium for Testing and Failure Analysis.Google ScholarCross Ref
- Swarup Bhunia and Mark Tehranipoo. 2019. Physical attacks and countermeasures. Hardware Security: A Hands-On Learning Approach.Elsevier, Amsterdam, 246--282.Google Scholar
- Adrian Stoica, Ricardo S. Zebulum, and Didier Keymeulen. 2001. Polymorphic electronics. In Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware (ICES’01). Springer-Verlag, London, 291--302.Google ScholarDigital Library
- Joshua Jaffe Paul Kocher and Benjamin Jun. 1998. Introduction to Differential Power Analysis and Related Attacks, 1998. Retrieved from http://www.cryptography.com/dpa/technical.Google Scholar
- Shahin Tajik, Heiko Lohrke, Jean-Pierre Seifert, and Christian Boit. 2017. On the power of optical contactless probing: Attacking bitstream encryption of FPGAs. In Proceedings of the ACM SIGSAC Conference on Computer and Communications Security.Google ScholarDigital Library
- Eli Biham and Adi Shamir. 1997. Differential fault analysis of secret key cryptosystems. In Proceedings of the Annual Conference on Advances in Cryptology (CRYPTO’97), Burton S. Kaliski (Ed.). Springer, Berlin, 513--525.Google ScholarCross Ref
- K. Sakiyama, Y. Li, M. Iwamoto, and K. Ohta. 2012. Information-theoretic approach to optimal differential fault analysis. IEEE Trans. Inf. Forens. Secur. 7, 1 (2012), 109--120.Google ScholarDigital Library
- Christophe Giraud. 2005. DFA on AES. In Advanced Encryption Standard—AES, Hans Dobbertin, Vincent Rijmen, and Aleksandra Sowa (Eds.). Springer, Berlin, 27--41.Google Scholar
- Subidh Ali, Xiaofei Guo, Ramesh Karri, and Debdeep Mukhopadhyay. 2016. Fault Attacks on AES and Their Countermeasures. Springer International Publishing, Cham, 163--208. DOI:http://dx.doi.org/10.1007/978-3-319-14971-4_5Google Scholar
- Manipatruni S. et al. 2019. Scalable energy-efficient magnetoelectric spin--orbit logic. Nature 565, 7737 (2019), 35--42.Google Scholar
- Nikonov D. E. Manipatruni S. and Young I. A. 2018. Beyond CMOS computing with spin and polarization. Nature Phys. 14 (2018).Google Scholar
- Sasikanth Manipatruni, Dmitri E. Nikonov, Ramamoorthy Ramesh, Huichu Li, and Ian A. Young. 2015. Spin-Orbit Logic with Magnetoelectric Nodes: A Scalable Charge Mediated Nonvolatile Spintronic Logic. arxiv:1512.05428. Retrieved from https://arxiv.org/abs/1512.05428.Google Scholar
- Sasikanth Manipatruni, Dmitri E. Nikonov, Huichu Liu, and Ian A. Young. 2017. Response to Comment on ‘Spin-Orbit Logic with Magnetoelectric Nodes: A Scalable Charge Mediated Nonvolatile Spintronic Logic.’ arXiv:1607.06690. Retrieved from https://arxiv.org/abs/1607.06690.Google Scholar
- Z. Liang, M. G. Mankalale, J. Hu, Z. Zhao, J. Wang, and S. S. Sapatnekar. 2018. Performance characterization and majority gate design for MESO-based circuits. IEEE J. Expl. Solid-State Comput. Devices Circ. 4, 2 (2018).Google Scholar
- L. Amarú, P. Gaillardon, and G. De Micheli. 2014. Majority-inverter graph: A novel data-structure and algorithms for efficient logic optimization. In Proceedings of the 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14). 1--6.Google Scholar
- L. Amarú, P. Gaillardon, and G. De Micheli. 2015. Boolean logic optimization in majority-inverter graphs. In Proceedings of the 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC’15). 1--6.Google Scholar
Index Terms
- Resilient and Secure Hardware Devices Using ASL
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