Supplemental Material
Available for Download
- 1.D. Brooks and M. Martonosi, "Dynamically Exploiting Narrow Width Operands to Improve Porcessor Power and Performance", in Proc. of 5th. Int. Symp. on High-Perf. Comp. Arch., 1999. Google ScholarDigital Library
- 2.D. Burger, T.M. Austin, S. Bennett, Evaluating Future Microprocessors: The SimpleScalar Tool Set, Technical Report CS-TR-96-1308, University of Wisconsin-Madison.Google Scholar
- 3.G. Cai and C.H. Lim, Architectural Level Power/ Performance Optimization and Dynamic Power Estimation, in the Cool Chips tutorial of the 32nd Int. Symp. on Microarchitecture 1999.Google Scholar
- 4.K.D. Kissell, MIPS16: High-density MIPS for the Embedded Market, SGI MIPS group, 1997.Google Scholar
- 5.M. Kozuch and A. Wolfe, Compression of Embedded Systems Programs, in Proc. of the Int. Conf. on Computer Design, 1994 Google ScholarDigital Library
- 6.C. Lee, M. Potkonjak and W. H. Mangione-Smith, Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, in Proc. of the 30th Int. Symp. on Microarch., Dec. 1997, pp. 330-335. Google ScholarDigital Library
- 7.C.R Lefurgy, E.M Piccininni and Trevor N Mudge, Evaluation of a High Performance Code Compression Method, in Proc. of the 32nd Int. Symp. on Microarchitecture 1999. Google ScholarDigital Library
- 8.J. Montanaro and et al. A 160-MHz, 32-b, 0.5 W CMOS RISC Microprocessor, Digital Tech. J'rnal, v.9. Dec, 1997. Google ScholarDigital Library
- 9.E. Musoll, Predicting the usefulness of a block result: a micro-architectural technique for high-performance lowpower processors, in Proc. of the 32nd Int. Symp. on Microarchitecture 1999. Google ScholarDigital Library
- 10.PowerPC 405CR User Manual, IBM/Motorola, 6/2000.Google Scholar
- 11.C. Price, MIPS IV Instruction Set, MIPS Tech. Inc, 1995.Google Scholar
- 12.J. Turley, Thumb Squeezes Arm Code Size, Microprocessor Report, vol 9. n. 4, March 1995.Google Scholar
- 13.J. Turley, PowerPC Adopts Code Compression, Microprocessor Report, October 1998.Google Scholar
- 14.S. Manne, A. Klauser and D. Grunwald, Pipeline Gating: Speculation Control for Energy Reduction, in Proc. of the 25 th Int. Symp on Comp. Arch. ,June 1998, pp.132-141. Google ScholarDigital Library
- 15.T. Sato and I. Arita, Table Size Reduction for Data Value Predictors by Exploiting Narrow Width Values, in Proc. of the 2000 Int. Conf. on Supercomp., May 2000, pp.196-205. Google ScholarDigital Library
- 16.N. Vijaykrishnan, M. Kandemir, M.J. Irwin, S.H. Kim and W. Ye, Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower, in Proc. of the 27 th Int. Symp on Comp. Architecture, 2000, pp. 95-106. Google ScholarDigital Library
- 17.T. Wada, S. Rajan and S. Przybylski, An Analytical Access Time Model for On-Chip Cache Memories, IEEE Journal of Solid-State Circuits, v.27, n. 8, pp. 1147-1156, Aug. 1992Google Scholar
- 18.A. Wolfe and A. Channin, Executing Compressed Programs on an Embedded RISC Architecture, in Proc. of the 19th Int. Symp. on Microarchitecture, 1992. Google ScholarDigital Library
Index Terms
- Very low power pipelines using significance compression
Recommendations
Low-complexity and low-memory entropy coder for image compression
A low-complexity and low-memory entropy coder (LLEC) is proposed for image compression. The two key elements in the LLEC are zerotree coding and Golomb-Rice (1966, 1991) codes. Zerotree coding exploits the zerotree structure of transformed coefficients ...
Bipartition architecture for low power JPEG Huffman decoder
ACSAC'07: Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems ArchitectureJPEG codec in portable device has become a popular technique nowadays. Because the portable device is battery powered, reducing power dissipation is practical. In this paper, a low power design technique for implementing JPEG Huffman decoder is ...
Power balanced pipelines
HPCA '12: Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer ArchitectureSince the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been a primary design objective, as it maximizes instruction throughput. ...
Comments